eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interface Overview 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for the eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interface Overview
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for the eCPRI Intel® FPGA IP User Guide

2.2.1. Reference and System PLL Clock for your IP Design

Each F-Tile system must instantiate one F-Tile Reference and System PLL Clocks Intel FPGA IP.
The F-Tile Reference and System PLL Clocks Intel FPGA IP performs three main functions:
  1. Configure reference clock for FHT PMA:
    • Enable the FHT common PLLs and select the reference clock source for FHT common PLL
    • Specify the FHT reference clock source frequency
  2. Configure reference clock for FGT PMA:
    • Enable FGT reference clocks and specify the reference clock frequency
    • Specify FGT CDR output
  3. Configure system PLL:
    • Enable system PLL and specify its mode
    • Specify the reference clock source and frequency for system PLL
Note: In your IP design, you must include an F-Tile Reference and System PLL Clocks Intel FPGA IP core to pass logic generation flow.

The F-Tile Reference and System PLL Clocks Intel FPGA IP must always connect to a protocol based Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP cannot be compiled or simulated as a standalone IP. For more information on parameters and port list for F-Tile Reference and System PLL Clocks Intel FPGA IP core, refer to the F-Tile Architecture and PMA/FEC Direct PHY IP User Guide.

When you design multiple interfaces or protocol-based IP within a single F-Tile, you must use only one instance of the F-Tile Reference and System PLL Clocks Intel FPGA IP to configure:
  • All required reference clocks for FGT PMA (up to 10) and FHT PMA (up to 2) to implement multiple interfaces within a single F-Tile.
  • All required FHT common PLLs (up to 2) to implement multiple interfaces within a single F-Tile.
  • All required System PLLs (up to 3) to implement multiple interfaces within a single F-Tile.
  • All required reference clocks for system PLLs (up to 8 – shared with FGT PMA) to implement multiple interfaces within a single F-Tile.

When you design multiple interfaces or protocol-based IP cores within a single F-Tile, you can only use three System PLLs. For example, you can use one System PLL for PCIe and two for Ethernet and other protocols. However, there are other use cases where you can use all three for various interfaces within the Ethernet and PMA-Direct digital blocks. As there are only three System PLLs, multiple interfaces or protocol-based IP cores with different line rates may have to share a System PLL. While sharing a System PLL, the interface with the highest line rate determines the system PLL frequency, and the interfaces with the lower line rates must be overclocked. For more information, refer to the F-Tile Architecture and PMA/FEC Direct PHY IP User Guide.

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