Visible to Intel only — GUID: kqd1583884569859
Ixiasoft
Visible to Intel only — GUID: kqd1583884569859
Ixiasoft
5.10. External ST Sink Interface
Signal Name | Width (Bits) | I/O Direction | Description |
---|---|---|---|
ext_sink_0_valid | 1 | Input | Avalon® sink valid from external user logic to L2/L3 parser. User must not drop valid between sop and eop. The only exception is when the ext_sink_0_ready signal deasserts, and you are required to deassert ext_sink_0_valid for three cycles of READY_LATENCY. |
ext_sink_0_data | DATA_WIDTH | Input | Avalon® sink write data from external user logic to L2/L3 parser. |
ext_sink_0_sop | 1 | Input | Avalon® sink start of packet from external user logic to L2/L3 parser. Indicates the beginning of packet. |
ext_sink_0_eop | 1 | Input | Avalon® sink end of packet from external user logic to L2/L3 parser. Indicates the end of packet. |
ext_sink_0_empty | LOG2 (DATA_WIDTH/8) | Input | Avalon® sink empty from external user logic to L2/L3 parser. Indicates the number of symbols that are empty, that is, do not represent valid data. |
ext_sink_0_ready | 1 | Output | Avalon® sink ready driven from L2/L3 parser. Indicate L2/L3 parser can accept data. |
ext_sink_0_error | 1 | Input | Avalon® sink error from external user logic to L2/L3 parser. A bit mask to mark errors affecting the data being transferred in the current cycle. |
ext_sink_0_timestamp_request_fingerprint | PTP_TS_FP_WIDTH | Input | Provides the fingerprint of the V2-format 1588 PTP frame currently beginning transmission on the Ethernet link. Value is valid when the ext_sink_0_sop and ext_sink_0_timestamp_request_valid signals are asserted. |
ext_sink_0_timestamp_request_valid | 1 | Input | Request valid for a timestamp for the transmit frame. This signal is asserted in the same clock cycle when the ext_sink_0_sop is asserted. Indicates that the ext_sink_0_timestamp_request_fingerprint signal is valid in the current ext_sink_clk clock. |
ext_sink_0_tx_egress_timestamp_96b_data | 96 | Output | Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the ext_sink_0_tx_egress_timestamp_96b_valid signal is asserted. |
ext_sink_0_tx_egress_timestamp_96b_valid | 1 | Output | Indicates that the ext_tx_egress_timestamp_96b_data signals are valid in the current ext_sink_clk clock cycle. This signal is meaningful only in the two step clock mode. |
ext_sink_0_tx_egress_timestamp_96b_fingerprint | PTP_TS_FP_WIDTH | Output | Fingerprint signal for current TX packet. Assigns a fingerprint to a TX packet that is being transmitted, so that the 2-step or 1-step PTP/eCPRI one way delay measurement timestamp associated with the TX packet can be identified. The timestamp returns with the same fingerprint. Valid only when the ext_sink_0_tx_egress_timestamp_96b_valid is asserted. |
ext_sink_0_tx_ingress_timestamp_96b_data | 96 | Input | Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the ext_sink_0_sop signal is asserted. |
ext_sink_1_valid | 1 | Input | Avalon® sink valid from external user logic to L2/L3 parser. User must not drop valid between sop and eop. The only exception is when the ext_sink_1_ready signal deasserts, and you are required to deassert ext_sink_1_valid for three cycles of READY_LATENCY. |
ext_sink_1_data | DATA_WIDTH | Input | Avalon® sink write data from external user logic to L2/L3 parser. |
ext_sink_1_sop | 1 | Input | Avalon® sink start of packet from external user logic to L2/L3 parser. Indicate the beginning of packet. |
ext_sink_1_eop | 1 | Input | Avalon® sink end of packet from external user logic to L2/L3 parser. Indicate the end of packet. |
ext_sink_1_empty | LOG2 (DATA_WIDTH/8) | Input | Avalon® sink empty from external user logic to L2/L3 parser. Indicates the number of symbols that are empty, that is, do not represent valid data. |
ext_sink_1_ready | 1 | Output | Avalon® sink ready driven from L2/L3 parser. Indicate L2/L3 parser can accept data. |
ext_sink_1_error | 1 | Input | Avalon® sink error from external user logic to L2/L3 parser. A bit mask to mark errors affecting the data being transferred in the current cycle. |
ext_sink_1_timestamp_request_fingerprint | PTP_TS_FP_WIDTH | Input | Provides the fingerprint of the V2-format 1588 PTP frame currently beginning transmission on the Ethernet link. Value is valid when the ext_sink_1_sop and ext_sink_1_timestamp_request_valid signals are asserted. |
ext_sink_1_timestamp_request_valid | 1 | Input | Request valid for a timestamp for the transmit frame. This signal is asserted in the same clock cycle when the ext_sink_1_sop is asserted. Indicates that the ext_sink_1_timestamp_request_fingerprint signal is valid in the current ext_sink_clk clock. |
ext_ sink_1_tx_egress_timestamp_96b_data | 96 | Output | Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the ext_ sink_1_tx_egress_timestamp_96b_valid signal is asserted. |
ext_ sink_1_tx_egress_timestamp_96b_valid | 1 | Output | Indicates that the ext_tx_egress_timestamp_96b_data signals are valid in the current ext_sink_clk clock cycle. This signal is meaningful only in a two-step clock mode. |
ext_ sink_1_tx_egress_timestamp_96b_fingerprint | PTP_TS_FP_WIDTH | Output | Fingerprint signal for current TX packet. Assigns fingerprint to a TX packet that is being transmitted, so that the 2-step or 1-step PTP/eCPRI one way delay measurement timestamp associated with the TX packet can be identified. The timestamp returns with the same fingerprint. Valid only when the ext_ sink_1_tx_egress_timestamp_96b_valid is asserted. |
ext_ sink_1_tx_ingress_timestamp_96b_data | 96 | Input | Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the ext_sink_1_sop signal is asserted. |