eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interface Overview 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for the eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interface Overview
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for the eCPRI Intel® FPGA IP User Guide

4.1. Interfaces

The eCPRI Intel® FPGA IP supports several interfaces.

Clock and Reset Interface

The main interface for the clock and reset signals in the eCPRI IP.

Configuration Avalon® Memory-Mapped Interface

This interface provides access to the internal control and status registers of the eCPRI IP. This interface complies with Avalon® memory-mapped interface specification as defined in the Avalon® Interface Specifications.

External MAC Source Interface

This interface provides datapath from eCPRI IP to 25G Ethernet MAC IP. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

External MAC Sink Interface

This interface provides datapath from 25G Ethernet MAC IP to eCPRI IP. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

eCPRI IP Source Interface

This interface provides datapath from eCPRI IP to client logic. This interface includes a number of sideband signals which align with the Avalon® streaming interface clock. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

eCPRI IP Sink Interface

This interface provides datapath from client logic to eCPRI IP. This interface includes a number of sideband signals which align with the Avalon® streaming interface clock. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

IWF Type 0 eCPRI Source Interface

This interface provides datapath from eCPRI IP to IWF logic. This interface includes a number of sideband signals which align with the eCPRI IP source interface.

IWF Type 0 eCPRI Sink Interface

This interface provides datapath from IWF logic to eCPRI IP. This interface includes a number of sideband signals which align with the eCPRI IP source interface.

IWF Type 0 CPRI MAC Interface

This interface provides datapath from eCPRI IWF type 0 function to CPRI MAC. This interface consists of the following interfaces:

  • CPRI 32-bit IQ Data
  • CPRI 64-bit IQ Data
  • CPRI 32-bit Ctrl_AxC
  • CPRI 64-bit Ctrl_AxC
  • CPRI 32-bit Vendor Specific
  • CPRI 64-bit Vendor Specific
  • CPRI 32-bit Real-Time Vendor Specific
  • CPRI 64-bit Real-Time Vendor Specific
  • CPRI Gigabit Media Independent Interface (GMII)

External ST Source Interface

This interface provides datapath from eCPRI IP to client logic. This interface is a primary output interface for PTP and C&M messages. This interface complies with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications. This interface includes a number of sideband signals which align with the Avalon® streaming interface clock.

External ST Sink Interface

The IP has two external sink interfaces. These interfaces provide datapath from client logic to eCPRI IP. These interfaces are also primary inputs for PTP and C&M messages. These interfaces comply with Avalon® streaming interface specification as defined in the Avalon® Interface Specifications.

TX and RX Time-of-Day (TOD) Interface

This interface provides 96-bit timestamp from PTP module to eCPRI IP core and to client logic.

Figure 6. eCPRI Intel® FPGA IP High-Level System Diagram
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