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1.2.1. Prerequisites
1.2.2. Getting Started
1.2.3. Generating the Initial HDL in Platform Designer (Standard)
1.2.4. Top Level Routing
1.2.5. Timing Constraint Configuration
1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition
1.2.7. Hardware Programming File Compilation and Generation
1.2.8. SD Card Image Updates
1.2.9. Board Setup and Booting Linux from the SD Card
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1.2.8.2. U-boot Setup
Go to file location u-boot-socfpga/include/configs/socfpga_cyclone.h. The EMAC0 parameters associated with the interface speed must be configured to MII in the socfpga_cyclone.h file in the u-boot source. Change the #define for CONFIG_EMAC_BASE and CONFIG_PHY_INTERFACE_MODE to the following:
#define CONFIG_EMAC_BASE CONFIG_EMAC0_BASE
#define CONFIG_PHY_INTERFACE_MODE SOCFPGA_PHYSEL_ENUM_MII
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