AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.2.4. Top Level Routing

The top level RTL file defines the pin connections from the Cyclone® V HPS EMAC0 to the Renesas MII PHY on the Cyclone® V SoC development board.
Note: Because MII is a 4-bit data width protocol, connect only the lower 4-bits, emac0_phy_txd_o[3:0] and emac0_phy_rxd_i[3:0], of EMAC0's RX and TX interface from the FPGA.
Figure 6. Routing of the EMAC0 FPGA Interface to the On-board MII PHY

HPS I2C0 is routed through the FPGA interface and acts as a master to various on-board I2C slaves:

  • Two Octal Digital Power Supply Managers with EEPROM
  • LCD
  • RTC
  • EEPROM
Note: A bi-directional buffer, ALT_IOBUF, must be added in the design to connect the I2C signals to an external open drain IO. The buffer can be included by instantiating ALT_IOBUF in ghrd_top.v.

The following Verilog code shows the ALT_IOBUF instantiation for an I2C interface implemented through the FPGA: 


ALT_IOBUF scl_iobuf (.i(1'b0), .oe(scl_o_e), .o(scl_o), .io(fpga_i2c_scl)); //declared bi-directional buffer for scl
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(sda_o_e), .o(sda_o), .io(fpga_i2c_sda)); //declared bi-directional buffer for sda
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