AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

The Intel Cyclone® V and Arria® V SoC device families integrate an Arm* Cortex* -A9-based hard processor system (HPS) consisting of processor, peripherals, and memory interface with the FPGA fabric using a high-bandwidth interconnect backbone. The Cyclone® V HPS interface provides up to 67 I/O pins to share with multiple peripherals through sets of configurable multiplexers. The Arria® V HPS interface provides up to 71 I/O pins.

This application note describes the steps required to route an HPS peripheral through the FPGA interface using Platform Designer (Standard) and Intel® Quartus® Prime Standard Edition software. A simple design example is included to demonstrate exporting HPS EMAC0 and I2C0 peripheral signals to the FPGA interface using a Cyclone® V SoC Development Kit.

Section Content
Cyclone V and Arria V HPS Peripherals That Support Routing to the FPGA
Design Example: Cyclone V HPS IP Interface to FPGA
Sample Application Example
Reference Documents
AN 706 Revision History

Level Two Title