AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:

  • Receiver data link layer
  • Receiver transport layer
  • Descrambling
  • Deterministic latency (Subclass 1)
Level Two Title