AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Date Version Changes
December 2017 2017.12.18
  • Renamed the document as AN 810: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report.
  • Added a note to clarify that the IOPLL input reference clock is sourcing from device clock through global clock network in the Hardware Setup topic.
  • Updated Figure: Deterministic Latency Test Setup Block Diagram.
  • Updated for latest branding standards.
  • Made editorial updates and restructuring to the document to improve clarity.
June 2017 2017.06.19 Initial release.
Level Two Title