AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Descrambling

The PRBS/Ramp checker at the receiver transport layer checks the data integrity of descrambler.

The Signal Tap Logic Analyzer tool monitors the operation of the receiver transport layer.

Table 4.  Descrambler Test Cases
Test Case Objective Description Passing Criteria

SCR.1

 Check the functionality of the descrambler using Ramp test pattern.

Enable scrambler at the ADC and descrambler at the JESD204B receiver IP Core.

The signals that are tapped in this test case are similar to test case TL.1
  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

SCR.2

 Check the functionality of the descrambler using PRBS-9 test pattern.

Enable scrambler at the ADC and descrambler at the JESD204B receiver IP Core.

The signals that are tapped in this test case are similar to test case TL.2
  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.
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