AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Code Group Synchronization (CGS)

Table 1.  CGS Test Cases
Test Case Objective Description Passing Criteria

CGS.1

Check whether sync request is de-asserted after correct reception of four successive /K/ characters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0]
  • jesd204_rx_pcs_kchar_data[(L*4)-1:0] 1

The following signals in <ip_variant_name>.v are tapped:

  • rx_dev_sync_n
  • jesd204_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data signal. The 32-bit data bus for is divided into 4 octets.

  • /K/ character or K28.5 (0xBC) is observed at each octet of the jesd204_rx_pcs_data bus.
  • The jesd204_rx_pcs_data_valid signal is asserted to indicate data from the PCS is valid.
  • The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ characters are observed.
  • The rx_dev_sync_n signal is de-asserted after correct reception of at least four successive /K/ characters.
  • The jesd204_rx_int signal is deasserted if there is no error.

CGS.2

Check full CGS at the receiver after correct reception of another four 8B/10B characters.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_rx_pcs_errdetect[(L*4)-1:0]
  • jesd204_rx_pcs_disperr[(L*4)-1:0] 1

The following signals in <ip_variant_name>.v are tapped:

  • jesd204_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

The jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr and jesd204_rx_int signals should not be asserted during CGS phase.

1 L is the number of lanes.
Level Two Title