Serial Lite IV Intel® FPGA IP User Guide

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ID 683655
Date 2/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® FPGA IP User Guide 2. Serial Lite IV Intel® FPGA IP Overview 3. Functional Description 4. Getting Started 5. Parameters 6. Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with Serial Lite IV Intel® FPGA IP 8. Serial Lite IV Intel® FPGA IP Registers 9. Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Functional Description x
3.1. TX Datapath 3.2. RX Datapath 3.3. Serial Lite IV Intel® FPGA IP Clock Architecture 3.4. Reset and Link Initialization 3.5. Link Rate and Bandwidth Efficiency Calculation
3.1. TX Datapath x
3.1.1. TX MAC Adapter 3.1.2. Control Word (CW) Insertion 3.1.3. TX CRC 3.1.4. TX MII Encoder 3.1.5. TX PCS and PMA
3.1.2. Control Word (CW) Insertion x
3.1.2.1. Start-of-burst CW 3.1.2.2. End-of-burst CW 3.1.2.3. Alignment Paired CW 3.1.2.4. Empty-cycle CW 3.1.2.5. Idle CW 3.1.2.6. Data Word
3.2. RX Datapath x
3.2.1. RX PCS and PMA 3.2.2. RX MII Decoder 3.2.3. RX CRC 3.2.4. RX Deskew 3.2.5. RX CW Removal
3.4. Reset and Link Initialization x
3.4.1. TX Reset and Initialization Sequence 3.4.2. RX Reset and Initialization Sequence 3.4.3. PMA Adaptation Flow
3.4.3. PMA Adaptation Flow x
3.4.3.1. Starting the PMA Adaptation Flow
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Simulating Intel® FPGA IP Cores 4.5. Synthesizing IP Cores in Other EDA Tools 4.6. Compiling the Full Design
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.4. Simulating Intel® FPGA IP Cores x
4.4.1. Simulating and Verifying the Design
6. Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. E-Tile Channel Placement Tool
1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

3.4.3.1. Starting the PMA Adaptation Flow

For E-tile Serial Lite IV Intel FPGA IP core variations, perform the following steps to start the PMA adaptation:

  1. Assert the TX, RX Digital Resets (tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n) and reconfiguration reset (reconfig_reset) signals. Release the reconfiguration reset (reconfig_reset) signal.
  2. Trigger the PMA analog reset and re-load the initial PMA settings.
    1. Write 0x200[7:0] = 0x00.
    2. Write 0x201[7:0] = 0x00.
    3. Write 0x202[7:0] = 0x00.
    4. Write 0x203[7:0] = 0x81.
    5. Read 0x207 until it becomes 0x80. This indicates that the operation completed successfully.
    6. Write 0x91[0] = 1 to load the initial settings in the programming file.
  3. Apply the control status registers (CSR) Reset (csr_phy_reset_n) signal and de-assert the CSR Reset (csr_phy_reset_n) signal.
  4. De-assert the TX Digital reset (tx_pcs_fec_phy_reset_n) and (tx_core_rst_n) signals.
  5. Configure the Attenuation Value (VOD) (skip this step if using internal serial loopback).
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x40.
    3. Write 0x86[7:0] = 0x15.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B [0] until it changes to 0.
    8. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.
  6. Set the operation mode, enable Internal Serial Loopback Mode via PMA attribute code. Attribute = 0x8, data = 0x101.
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x01.
    3. Write 0x86[7:0] = 0x08.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  7. Perform Initial Adaptation in Serial Loopback Mode. Attribute = 0xA, data = 0x1.
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x0A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  8. Verify that the initial adaptation status is complete using interrupt code. Attribute = 0x0126, data = 0x0B00.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x0B.
    3. Write 0x86[7:0] = 0x26.
    4. Write 0x87[7:0] = 0x01.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
    9. Read register 0x88. Repeat Step 8 until 0x88[0] = 0, to confirm that adaptation is no longer in process.
  9. Enable mission mode and disable internal serial loopback (skip this step if using internal serial loopback). Attribute = 0x8, data = 0x100.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x01.
    3. Write 0x86[7:0] = 0x08.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  10. Run initial adaptation via PMA attribute code (skip this step if using internal serial loopback). Attribute = 0xA, data = 0x1.
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x0A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  11. Verify that the initial adaptation status is complete using interrupt code (skip this step if using internal serial loopback). Attribute = 0x0126, data = 0x0B00.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x0B.
    3. Write 0x86[7:0] = 0x26.
    4. Write 0x87[7:0] = 0x01.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
    9. Read register 0x88. Repeat Step 11 until 0x88[0] = 0, to confirm that adaptation is no longer in process.
  12. Perform Continuous adaptation via PMA attribute code (skip this step if using internal serial loopback). Attribute = 0xA, data = 0x6.
    1. Write 0x84[7:0] = 0x06.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x0A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  13. De-assert RX Digital reset (rx_pcs_fec_phy_reset_n) and (rx_core_rst_n) signals.
  14. Verify that the link status signals (tx_link_up) and (rx_link_up) transitions high. If the link status signals are not high, repeat all the steps above.
  15. Send packets.
Figure 25. Reset and Adaptation Flow Sequence
Level Two Title