Serial Lite IV Intel® FPGA IP User Guide

Download PDF
ID 683655
Date 2/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® FPGA IP User Guide 2. Serial Lite IV Intel® FPGA IP Overview 3. Functional Description 4. Getting Started 5. Parameters 6. Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with Serial Lite IV Intel® FPGA IP 8. Serial Lite IV Intel® FPGA IP Registers 9. Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Functional Description x
3.1. TX Datapath 3.2. RX Datapath 3.3. Serial Lite IV Intel® FPGA IP Clock Architecture 3.4. Reset and Link Initialization 3.5. Link Rate and Bandwidth Efficiency Calculation
3.1. TX Datapath x
3.1.1. TX MAC Adapter 3.1.2. Control Word (CW) Insertion 3.1.3. TX CRC 3.1.4. TX MII Encoder 3.1.5. TX PCS and PMA
3.1.2. Control Word (CW) Insertion x
3.1.2.1. Start-of-burst CW 3.1.2.2. End-of-burst CW 3.1.2.3. Alignment Paired CW 3.1.2.4. Empty-cycle CW 3.1.2.5. Idle CW 3.1.2.6. Data Word
3.2. RX Datapath x
3.2.1. RX PCS and PMA 3.2.2. RX MII Decoder 3.2.3. RX CRC 3.2.4. RX Deskew 3.2.5. RX CW Removal
3.4. Reset and Link Initialization x
3.4.1. TX Reset and Initialization Sequence 3.4.2. RX Reset and Initialization Sequence 3.4.3. PMA Adaptation Flow
3.4.3. PMA Adaptation Flow x
3.4.3.1. Starting the PMA Adaptation Flow
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Simulating Intel® FPGA IP Cores 4.5. Synthesizing IP Cores in Other EDA Tools 4.6. Compiling the Full Design
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.4. Simulating Intel® FPGA IP Cores x
4.4.1. Simulating and Verifying the Design
6. Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. E-Tile Channel Placement Tool
1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

6.4. Transceiver Reconfiguration Signals

Table 26.  PCS Reconfiguration SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description

phy_reconfig_read

N/2 (PAM4 mode)

N (NRZ mode)

Input reconfig_clk PCS reconfiguration read command signals.

phy_reconfig_write

N/2 (PAM4 mode)

N (NRZ mode)

Input reconfig_clk PCS reconfiguration write command signals.

phy_reconfig_address

21*(N/2) (PAM4 mode)

19*N (NRZ mode)

Input reconfig_clk Specifies PCS reconfiguration Avalon memory-mapped interface address in a selected lane.

For NRZ mode, each lane has 19 bits and lane 0 address starts from phy_reconfig_address[18:0].

Example, for a 4-lane NRZ design:
  • phy_reconfig_address[18:0] = address for lane 0.
  • phy_reconfig_address[37:19] = address for lane 1.
  • phy_reconfig_address[56:38] = address for lane 2.
  • phy_reconfig_address[75:57] = address for lane 3.

For PAM4 mode, the lower 19 bits within the 21-bit bus specify the address and the upper 2 bits specify the lane.

Example, for a 4-lane PAM4 design:
  • phy_reconfig_address[18:0] = address for lane 0 and 1, phy_reconfig_address[20:19] = lane number 0 and 1.
  • phy_reconfig_address[39:21] = address for lane 2 and 3, phy_reconfig_address[41:40] = lane number 2 and 3.

phy_reconfig_readdata

32*(N/2)

32*N (NRZ mode)

Output reconfig_clk Specifies PCS reconfiguration data to be read by a ready cycle in a selected lane.

phy_reconfig_waitrequest

N/2 (PAM4 mode)

N (NRZ mode)

Output reconfig_clk Represents PCS reconfiguration Avalon memory-mapped interface stalling signal in a selected lane.
phy_reconfig_writedata

32*(N/2) (PAM4 mode)

32*N (NRZ mode)

Input reconfig_clk Specifies PCS reconfiguration data to be written on a write cycle in a selected lane.
phy_reconfig_readdata_valid

N/2 (PAM4 mode)

N (NRZ mode)

Output reconfig_clk Specifies PCS reconfiguration received data is valid in a selected lane.
Table 27.  PMA Reconfiguration SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description
xcvr_reconfig_read

N*2 (PAM4 mode)

N (NRZ mode)

Input reconfig_clk PMA reconfiguration read command signals.
xcvr_reconfig_write

N*2 (PAM4 mode)

N (NRZ mode)

Input reconfig_clk PMA reconfiguration write command signals.
xcvr_reconfig_address

19*N*2 (PAM4 mode)

19*N (NRZ mode)

Input reconfig_clk Specifies PMA Avalon memory-mapped interface address in a selected lane.

In both PAM4 ad NRZ modes, each lane has 19 bits and lane 0 address starts from xcvr_reconfig_address[18:0].

Example, for a 4-lane design:
  • xcvr_reconfig_address[18:0] = address for lane 0.
  • xcvr_reconfig_address[37:19] = address for lane 1.
  • xcvr_reconfig_address[56:38] = address for lane 2.
  • xcvr_reconfig_address[75:57] = address for lane 3.
xcvr_reconfig_readdata

8*N*2 (PAM4 mode)

8*N (NRZ mode)

Output reconfig_clk Specifies PMA data to be read by a ready cycle in a selected lane.
xcvr_reconfig_waitrequest

N*2 (PAM4 mode)

N (NRZ mode)

Output reconfig_clk Represents PMA Avalon memory-mapped interface stalling signal in a selected lane.
xcvr_reconfig_writedata

8*N*2 (PAM4 mode)

8*N (NRZ mode)

Input reconfig_clk Specifies PMA data to be written on a write cycle in a selected lane.
Table 28.  RS-FEC Reconfiguration Signals
Name Width Direction Clock Domain Description
rsfec_reconfig_read 1 Input reconfig_clk RS-FEC reconfiguration read command signal.
rsfec_reconfig_write 1 Input reconfig_clk RS-FEC reconfiguration write command signal.
rsfec_reconfig_address

11 + lane offset

 Input reconfig_clk Specifies RS-FEC reconfiguration Avalon memory-mapped interface address.
For PAM4 mode:
  • If N/2 = 1, lane offset is 0
  • If N/2 = 2, lane offset is 1
  • If N/2 = 3, lane offset is 2
  • If N/2 = 4, lane offset is 2
For NRZ mode:
  • For number of lanes from 1 to 4, the lane offset is 0.
  • For number of lanes from 5 to 8, the lane offset is 1.
  • For number of lanes from 9 to 16, the lane offset is 2.
rsfec_reconfig_readdata 8 Output reconfig_clk Specifies RS-FEC reconfiguration data to be read by a ready cycle in a selected lane.
rsfec_reconfig_waitrequest 1 Output reconfig_clk Represents RS-FEC reconfiguration Avalon memory-mapped interface stalling signal in a selected lane.
rsfec_reconfig_writedata 8 Input reconfig_clk Specifies RS-FEC reconfiguration data to be written on a write cycle in a selected lane.
Level Two Title