Serial Lite IV Intel® FPGA IP User Guide

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ID 683655
Date 2/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® FPGA IP User Guide 2. Serial Lite IV Intel® FPGA IP Overview 3. Functional Description 4. Getting Started 5. Parameters 6. Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with Serial Lite IV Intel® FPGA IP 8. Serial Lite IV Intel® FPGA IP Registers 9. Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Functional Description x
3.1. TX Datapath 3.2. RX Datapath 3.3. Serial Lite IV Intel® FPGA IP Clock Architecture 3.4. Reset and Link Initialization 3.5. Link Rate and Bandwidth Efficiency Calculation
3.1. TX Datapath x
3.1.1. TX MAC Adapter 3.1.2. Control Word (CW) Insertion 3.1.3. TX CRC 3.1.4. TX MII Encoder 3.1.5. TX PCS and PMA
3.1.2. Control Word (CW) Insertion x
3.1.2.1. Start-of-burst CW 3.1.2.2. End-of-burst CW 3.1.2.3. Alignment Paired CW 3.1.2.4. Empty-cycle CW 3.1.2.5. Idle CW 3.1.2.6. Data Word
3.2. RX Datapath x
3.2.1. RX PCS and PMA 3.2.2. RX MII Decoder 3.2.3. RX CRC 3.2.4. RX Deskew 3.2.5. RX CW Removal
3.4. Reset and Link Initialization x
3.4.1. TX Reset and Initialization Sequence 3.4.2. RX Reset and Initialization Sequence 3.4.3. PMA Adaptation Flow
3.4.3. PMA Adaptation Flow x
3.4.3.1. Starting the PMA Adaptation Flow
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Simulating Intel® FPGA IP Cores 4.5. Synthesizing IP Cores in Other EDA Tools 4.6. Compiling the Full Design
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.4. Simulating Intel® FPGA IP Cores x
4.4.1. Simulating and Verifying the Design
6. Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. E-Tile Channel Placement Tool
1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

6.5. PMA Signals

Table 29.  PMA SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description

phy_tx_lanes_stable

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates TX datapath is ready to send data.

tx_pll_locked

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates the TX PLL has achieved lock status.

phy_ehip_ready

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates that the custom PCS has completed internal initialization and ready for transmission.

This signal asserts after tx_pcs_fec_phy_reset_n and tx_pcs_fec_phy_reset_nare deasserted.

tx_serial_data

N*2 (PAM4 mode)

N (NRZ mode)

Output TX serial clock TX serial pins.

rx_serial_data

N*2 (PAM4 mode)

N (NRZ mode)

Input RX serial clock RX serial pins.
phy_rx_block_lock

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates that the 66b block alignment has completed for the lanes.
rx_cdr_lock

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates that the recovered clocks are locked to data.
phy_rx_pcs_ready

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates that the RX lanes of the corresponding Ethernet channel are fully aligned and ready to receive data.
phy_rx_hi_ber

N*2 (PAM4 mode)

N (NRZ mode)

Output Asynchronous When asserted, indicates that the RX PCS of the corresponding Ethernet channel is in a HI BER state.
Level Two Title