Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 2/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.02.10 22.4 4.0.0
  • Added topic: Starting the PMA Adaptation Flow.
  • Updated Table: Reset Signals
  • Updated Table: Serial Lite IV Intel FPGA IP Release Information
  • Updated Table: IP Version and Support Level
2022.11.11 21.3 1.3.1
  • Updated Figure: RX Reset and Initialization Timing Diagram
  • Updated Serial Lite IV Intel® FPGA IP User Guide Archives
2021.12.01 21.3 1.3.1
  • Added new Table: Signal Mapping Between Serial Lite IV Intel® FPGA IP and E-Tile Hard IP for Ethernet Intel® FPGA IP .
  • Corrected the Transceiver data rate values for NRZ with RS-FEC enabled mode in Table: IP from "10.3125 Gbps to 28.0 Gbps" to "10.000 Gbps to 28.0 Gbps".
2021.11.01 21.3 1.3.1 Added support for QuestaSim* simulator.
2021.10.04 21.2 1.3.1
  • Updated the guideline for error condition during deskew process in Table: Error Condition and Handling Guidelines.
2021.08.18 21.2 1.3.1
  • Updated the following topics:
    • TX Reset and Initialization Sequence
    • RX Reset and Initialization Sequence
  • Updated the following Figures: RX Reset and Initialization Timing Diagram and TX Reset and Initialization Timing Diagram.
  • Corrected the description for reconfig_reset to clarify that this signal is an active-high reset signal in Table: Reset Signals.
  • Removed support for NCSim in the following tables:
    • Table: Serial Lite IV IP Core Generated Files
    • Table: Intel FPGA IP Core Simulation Scripts
2021.04.09 21.1 1.3.1
  • Updated RX Reset and Initialization Sequence.
  • Made minor editorial edits to the document.
2021.04.01 21.1 1.3.1
  • Added new parameters to Table: IP:
    • Preserve unused transceiver channels for PAM4
    • Reference clock frequency for preserved channels
  • Updated the Transceiver data rate value for PAM4 mode in Table: IP from 32.0 Gbps to 32.5 Gbps.
  • Added a new interface signal—xcvr_ref_clk_1.
  • Updated the following tables:
    • Serial Lite IV Intel® FPGA IP Release Information
    • IP Version and Support Level
2020.03.12 19.4 1.2.0
  • Updated effective rates for PAM4 transceiver mode in the Bandwidth Efficiency table.
  • Removed the effective rate calculation for PAM4 in the Link Rate and Bandwidth Efficiency Calculation topic.
  • Added PMA Adaptation Flow topic and link to the Ethernet Adaptation Flow with Non-external AIB Clocking in the E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs user guide.
2020.01.23 19.4 1.2.0
  • Added ALM count and IP latency for NRZ with RS-FEC enabled mode in the Intel® Stratix® 10 Serial Lite IV Intel FPGA IP Resource Utilization and Intel® Agilex™ Serial Lite IV Intel FPGA IP Resource Utilization tables.
  • Added bandwidth efficiency values for NRZ with RS-FEC enabled mode in the Bandwidth Efficiency table.
  • Updated the effective rate calculations for both NRZ and PAM4 features in the Link Rate and Bandwidth Efficiency Calculation topic.
  • Updated values for the following parameters in the Parameters topic:
    • Transceiver data rate
    • Set user-defined IP identifier
  • Updated rsfec_reconfig_address signals description for NRZ mode.
  • Added description to decode addresses and lane numbers for the phy_reconfig_address and xcvr_reconfig_address signals.
2019.09.30 19.3 1.1.0
  • Changed IP name to Serial Lite IV Intel FPGA IP.
  • Added support for Intel® Agilex™ devices.
  • Added support for NRZ mode.
  • Added information for CRC feature.
  • Updated PCS, PMA and RS-FEC reconfiguration signals width.
2019.07.01 19.2 1.0.0 Initial release.