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Ixiasoft
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Ixiasoft
1.1. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet
Arria® 10 and Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively. The Hard IP for PCI Express* using the Avalon® Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough understanding of the PCI Express* Protocol.
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga‑transfers per second for Gen3. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to about 1.5%.
Link Width | ||||
---|---|---|---|---|
×1 | ×2 | ×4 | ×8 | |
PCI Express Gen1 (2.5 Gbps) |
2 |
4 |
8 |
16 |
PCI Express Gen2 (5.0 Gbps) |
4 |
8 |
16 |
32 |
PCI Express Gen3 (8.0 Gbps) |
7.87 |
15.75 |
31.51 |
63 |
The following table shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 for 1, 2, and 4 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5.0 giga-transfers per second for Gen2. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.
Link Width | |||
---|---|---|---|
×1 | ×2 | ×4 | |
PCI Express Gen1 (2.5 Gbps) |
2 |
4 |
8 |
PCI Express Gen2 (5.0 Gbps) |
4 |
8 |
16 |
Refer to the AN 456: PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Intel FPGAs, including the Arria® 10 Hard IP for PCI Express IP core.
Devices