Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 9/11/2024
Public
Document Table of Contents

A.1. TLP Packet Formats without Data Payload

The following figures show the header format for TLPs without a data payload.

For more information about the alignment of 3- and 4-dword headers refer to the related links below for Data Alignment and Timing for the Avalon-ST TX and RX Interfaces.

Figure 110. Memory Read Request, 32-Bit Addressing
Figure 111. Memory Read Request, Locked 32-Bit Addressing
Figure 112. Memory Read Request, 64-Bit Addressing
Figure 113. Memory Read Request, Locked 64-Bit Addressing
Figure 114. Configuration Read Request Root Port (Type 1)
Figure 115. I/O Read Request
Figure 116. Message without Data

Figure 117. Completion without Data
Figure 118. Completion Locked without Data