Visible to Intel only — GUID: lbl1417712752955
Ixiasoft
Visible to Intel only — GUID: lbl1417712752955
Ixiasoft
1.1.1. Arria® 10 or Cyclone® 10 GX Features
New features in the Quartus® Prime 17.1 software release:
- Added Cyclone® 10 GX support for up to Gen2 x4 configurations.
- Added parameter to invert the RX polarity.
The Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express supports the following features:
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
- Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Native Endpoints in Arria® 10 devices.
- Support for ×1, ×2, and ×4 configurations with Gen1 or Gen2 lane rates for Native Endpoints in Cyclone® 10 GX devices.
- Dedicated 16 KB receive buffer.
- Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.
- Example designs demonstrating parameterization, design modules, and connectivity.
- Extended credit allocation settings to better optimize the RX buffer space based on application type.
- Support for multiple packets per cycle with the 256‑bit Avalon‑ST interface.
- Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
- Support for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported.
- Easy to use:
- Flexible configuration.
- Substantial on-chip resource savings and guaranteed timing closure.
- No license requirement.
- Example designs to get started.
Feature |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
IP Core License |
Free |
Free |
Free |
Native Endpoint |
Supported |
Supported |
Supported |
Root port |
Supported |
Supported |
Not Supported |
Gen1 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
Not Supported |
Gen2 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
×4, ×8 |
Gen3 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4 |
×2, ×4, ×8 |
64-bit Application Layer interface |
Supported |
Supported |
Not supported |
128-bit Application Layer interface |
Supported |
Supported |
Supported |
256‑bit Application Layer interface |
Supported |
Not Supported |
Supported |
Maximum payload size |
128, 256, 512, 1024, 2048 bytes |
128, 256 bytes |
128, 256 bytes |
Number of tags supported for non-posted requests |
32, 64, 128, 256 1 | 8 for 64-bit interface 16 for 128-bit interface |
16 or 256 |
Automatically handle out-of-order completions (transparent to the Application Layer) |
Not supported |
Supported |
Not Supported |
Automatically handle requests that cross 4 KB address boundary (transparent to the Application Layer) |
Not supported |
Supported |
Supported |
Polarity Inversion of PIPE interface signals |
Supported |
Supported |
Supported |
Number of MSI requests |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 |
MSI-X |
Supported |
Supported |
Supported |
Legacy interrupts |
Supported |
Supported |
Supported |
Expansion ROM |
Supported |
Not supported |
Not supported |
PCIe bifurcation | Not supported | Not supported | Not supported |
Transaction Layer Packet type (TLP) (transmit support) |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
Memory Read Request (Mrd) | EP/RP | EP/RP | EP |
Memory Read Lock Request (MRdLk) | EP/RP | EP | |
Memory Write Request (MWr) | EP/RP | EP/RP | EP |
I/O Read Request (IORd) | EP/RP | EP/RP | |
I/O Write Request (IOWr) | EP/RP | EP/RP | |
Config Type 0 Read Request (CfgRd0) | RP | RP | |
Config Type 0 Write Request (CfgWr0) | RP | RP | |
Config Type 1 Read Request (CfgRd1) | RP | RP | |
Config Type 1 Write Request (CfgWr1) | RP | RP | |
Message Request (Msg) | EP/RP | EP/RP | |
Message Request with Data (MsgD) | EP/RP | EP/RP | |
Completion (Cpl) | EP/RP | EP/RP | EP |
Completion with Data (CplD) | EP/RP | EP | |
Completion-Locked (CplLk) | EP/RP | ||
Completion Lock with Data (CplDLk) | EP/RP | ||
Fetch and Add AtomicOp Request (FetchAdd) | EP |
The Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.