Visible to Intel only — GUID: nik1410565000918
Ixiasoft
Visible to Intel only — GUID: nik1410565000918
Ixiasoft
16.1. Endpoint Testbench
After you install the Quartus® Prime software, you can copy any of the example designs from the <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 directory.
You can create an Endpoint design for inclusion in the testbench using design flows described in the Quick Start Guide. This testbench uses the parameters that you specify in the Quick Start Guide.
The top-level of the testbench instantiates the following main modules:
- altpcietb_bfm_rp_<gen>_x8.sv —This is the Root Port PCIe* BFM. This is the module that you modify to vary the transactions sent to the example Endpoint design or your own design.
//Directory path <project_dir>/pcie_<dev>_hip_ast_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/DUT_pcie_tb_ip/altera_pcie_<dev>_tbed_<ver>/sim
Note: If you modify the RP BFM, you must also make the appropriate corresponding changes the APPs module. - pcie_example_design_DUT.ip: This is the Endpoint design with the parameters that you specify.
//Directory path <project_dir>/pcie_<dev>_hip_ast_0_example_design/ip/pcie_example_design
- pcie_example_design_APPS.ip: This module is a target and initiator of transactions.
//Directory path <project_dir>/pcie_<dev>_hip_ast_0_example_design/ip/pcie_example_design/
- altpcietb_bfm_cfpb.v: This module supports Configuration Space Bypass mode. It drives TLPs to the custom Configuration Space.
//Directory path <project_dir>/pcie_<dev>_hip_ast_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/DUT_pcie_tb_ip/altera_pcie_<dev>_tbed_<ver>/sim
In addition, the testbench has routines that perform the following tasks:
- Generates the reference clock for the Endpoint at the required frequency.
- Provides a PCI Express reset at start up.