Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 9/11/2024
Public
Document Table of Contents

7. Reset and Clocks

The following figure shows the hard reset controller that is embedded inside the Hard IP for PCI Express* . This controller takes in the npor and pin_perst inputs and generates the internal reset signals for other modules in the Hard IP.

Figure 48. Reset Controller in Arria® 10 or Cyclone® 10 GX Devices

Note: If FLR is active or has yet to complete, avoid performing a warm reset or asserting pin_perst. Otherwise, the PCIe link may become unstable and will not be able to recover without a cold reset.
Note: The minimum interval time required between two consecutive pin_perst's or hot resets is 60us to ensure link stability. More specifically, the deassertion of pin_perst or hot reset, and the assertion of the next pin_perst or hot reset should be separated by at least 60us.