AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

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ID 683631
Date 1/12/2018
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Document Table of Contents
Document Table of Contents x
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Compiling the Reference Design 1.4. Hardware Setup 1.5. Generating Executable and Linking Format (.elf) Programming File 1.6. Running the Hardware Reference Design 1.7. Results 1.8. Reference Design Architecture 1.9. Document Revision History for AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
1.7. Results x
1.7.1. Random Data Transfer Result 1.7.2. Dynamic Calibration Result
1.8. Reference Design Architecture x
1.8.1. Functional Description PLL module dut_OUTPUT Module dut_INPUT Module Avalon Controller ATSO_DYN_CFG_CTRL with Nios II Processor Module Traffic Generator Module 1.8.2. Data Word Alignment Algorithm 1.8.3. Timing Analysis Guidelines
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

1.8.1. Functional Description

PLL module

This module takes the input from Si570 Programmable Oscillator and provides reference clock to the internal PLL modules in each of the Intel FPGA PHYLite for Parallel Interfaces IP cores.

dut_OUTPUT Module

This Intel FPGA PHYLite for Parallel Interfaces IP core transfers data from ATSO_DYN_CFG_CTRL or traffic generator module to dut_INPUT module. During configuration and calibration mode, this module takes data from ATSO_DYN_CFG_CTRL module and send to dut_INPUT module. In normal operating mode, this module takes data from traffic generator and sends to dut_INPUT module.

dut_INPUT Module

This Intel FPGA PHYLite for Parallel Interfaces IP core receives data from dut_OUTPUT module. This module sends the received data to ATSO_DYN_CFG_CTRL module during configuration and calibration mode, and to traffic generator during normal operating mode for data verification.

Avalon Controller

The Avalon controller is responsible to perform address translation to retrieve the physical address of the strobe and data pins and sends reconfiguration commands to dut_OUTPUT module.

ATSO_DYN_CFG_CTRL with Nios II Processor Module

This module consist of Nios II processor and five parallel I/O modules. This is a centralized controller to perform and manage dut_OUTPUT configuration. It also issues control signals to the Avalon controller and verify data from dut_INPUT during calibration mode.
Table 1.  Parallel I/O Modules - Function and Address Map
Parallel I/O Module Address Map Description
phy_write_data 0x20 Sends calibration test data to dut_OUTPUT module.
phy_write_ctrl 0x30 Asserts rdata_en signal during calibration mode.
phy_read_data 0x40 Receives data from dut_INPUT module for comparison against test data.
phy_read_status 0x50 Receives rdata_valid signal from dut_INPUT module.
cal_mode 0x60 Asserts cfg_done signal to exit calibration mode and activates traffic generator module for data transfer for normal operating mode.

Traffic Generator Module

Traffic Generator module is responsible for transmitting data to dut_OUTPUT and receiving data from dut_INPUT during normal operating mode. The module uses Linear Feedback Shift Register (LFSR) to generate random data for transmission. Traffic generator performs data comparison to the received data to ensure the strobe enable delay setting is configured correctly.

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