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Ixiasoft
Visible to Intel only — GUID: nik1411172556838
Ixiasoft
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores
Resource utilization changes depending on the parameter settings you specify in the Low Latency 40-100GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the LL 40-100GbE parameter editor, the IP core requires additional resources to implement the additional functionality.
40GbE Variation |
ALMs |
Dedicated Logic Registers |
Memory M20K |
---|---|---|---|
40GbE variation A |
5300 |
12800 |
13 |
40GbE variation B |
9900 |
21500 |
13 |
40GbE variation C | 10900 | 24100 | 13 |
40GbE variation D |
14000 |
31000 |
17 |
100GbE Variation |
ALMs |
Dedicated Logic Registers |
Memory M20K |
100GbE variation A |
9500 | 23000 | 29 |
100GbE variation B |
20900 | 48400 | 61 |
100GbE variation C | 22100 | 52500 | 61 |
100GbE variation D |
26900 | 63700 | 65 |