Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683628
Date 12/28/2017
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1 C. Additional Information
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Low Latency 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores 1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
2. Getting Started x
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices 2.2. Licensing IP Cores 2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. Low Latency 40-100GbE IP Core Testbenches 2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches 2.10. Compiling the Full Design and Programming the FPGA 2.11. Initializing the IP Core
2.2. Licensing IP Cores x
2.2.1. OpenCore Plus IP Evaluation
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.5. Clock Requirements for 40GBASE-KR4 Variations 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.8. Low Latency 40-100GbE IP Core Testbenches x
2.8.1. Low Latency 40-100GbE IP Core Testbench Overview 2.8.2. Understanding the Testbench Behavior
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches x
2.9.1. Generating the Low Latency 40-100GbE Testbench 2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches 2.9.3. Simulating with the Modelsim Simulator 2.9.4. Simulating with the NCSim Simulator 2.9.5. Simulating with the VCS Simulator 2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3. Functional Description x
3.1. High Level System Overview 3.2. Low Latency 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. Low Latency 40-100GbE MAC and PHY Functional Description x
3.2.1. Low Latency 40-100GbE IP Core TX Datapath 3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces 3.2.3. Low Latency 40-100GbE IP Core RX Datapath 3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Low Latency 40GBASE-KR4 IP Core Variations 3.2.18. Control and Status Interface 3.2.19. Arria 10 Transceiver Reconfiguration Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. Low Latency 40-100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. Low Latency 40-100GbE IP Core RX Datapath x
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. Pause Ignore 3.2.3.9. Control Frame Identification
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface x
3.2.4.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.4.2. Low Latency 40-100GbE IP Core RX Data Bus 3.2.4.3. Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 40-100GbE IP Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. Low Latency 40-100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. Low Latency 40-100GbE IP Core Registers 3.4.2. LL 40‑100GbE Hardware Design Example Registers
3.4.1. Low Latency 40-100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. Low Latency 40-100GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40‑100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
C. Additional Information x
C.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Archives C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History C.3. How to Contact Altera C.4. Typographic Conventions
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1
C. Additional Information

3.4.1.5. Pause Registers

The pause registers together with the pause signals implement the pause functionality defined in the IEEE 802.3ba-2010 100G Ethernet Standard. You can program the pause registers to control the insertion and decoding of pause frames, to help reduce traffic in congested networks.

Table 42.  TX Ethernet Flow Control (Pause Functionality) Registers Some registers are different depending on whether you select Standard flow control or Priority-based flow control in the Low Latency 40-100GbE parameter editor. Where the difference is only whether the register refers to the single standard flow control priority class or whether distinct bits in the register refer to the individual priority queues, the two uses are documented together. In that case we understand that standard flow control effectively supports a single priority queue.
When your IP core implements priority-based flow control, the following registers provide an access window into an internal table of values, one per priority queue. The entry currently accessible in the registers is determined by the value you write to the TX_PAUSE_QNUMBER register.
  • RETRANSMIT_XOFF_HOLDOFF_QUANTA at offset 0x608
  • TX_PAUSE_QUANTA at offset 0x609

Addr

Name

Bit

Description

HW Reset Value

Access

0x600 TXSFC_REVID [31:0] TX standard flow control module revision ID. 0x01282014 RO
0x601 TXSFC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x602 TXSFC_NAME_0 [31:0] First 4 characters of IP core variation identifier string "40GSFCTxCSR" or "100GSFCTxCSR". RO
0x603 TXSFC_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "40GSFCTxCSR" or "100GSFCTxCSR". RO
0x604 TXSFC_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "40GSFCTxCSR" or "100GSFCTxCSR". RO
0x605 TX_PAUSE_EN [N-1:0] 9 Enable the IP core to transmit pause frames on the Ethernet link in response to a client request through the pause_insert_tx input signal or the TX_PAUSE_REQUEST register. If your IP core implements priority-based flow control, each bit of this field enables TX pause functionality for the corresponding priority queue.

Altera recommends that you signal a pause request using the pause_insert_tx signal rather than using the TX_PAUSE_REQUEST register.

N'b1 ...1 (1'b1 in each defined bit) RW
0x606 TX_PAUSE_REQUEST [N-1:0]9

Pause request. If bit [n] of the TX_PAUSE_EN register has the value of 1, setting bit [n] of the TX_PAUSE_REQUEST register field to the value of 1 triggers a XOFF pause packet insertion into the TX data stream on the Ethernet link. If the IP core implements priority-based flow control, the XOFF pause packet includes identity information for the corresponding priority queue.

If RETRANSMIT_XOFF_HOLDOFF_EN is turned on for the associated priority queue, as long as the value in TX_PAUSE_REQUEST bit [n] remains high, the IP core retransmits the XOFF pause packet at intervals determined by the retransmit hold-off value associated with this priority queue.

If bit [n] of the TX_PAUSE_EN register has the value of 1, resetting bit [n] of the TX_PAUSE_REQUEST register field to the value of 0 triggers an XON pause packet insertion into the TX data stream on the Ethernet link. If the IP core implements priority-based flow control, the XON pause packet includes identity information for the corresponding priority queue.

Other pause registers, described in this table, specify the properties of the pause packets.

Altera recommends that you signal a pause request using the pause_insert_tx signal rather than using the TX_PAUSE_REQUEST register.

0 RW
0x607 RETRANSMIT_XOFF_HOLDOFF_EN [N-1:0] 9 Enable XOFF pause frame retransmission hold-off functionality. If your IP core implements priority-based flow control with multiple priority queues, this register provides access to one bit for each priority queue.

Altera recommends that you maintain this register at the value of all ones.

If your IP core implements priority-based flow control, refer also to the description of the CFG_RETRANSMIT_HOLDOFF_EN and CFG_RETRANSMIT_HOLDOFF_QUANTA registers.

N'b1...1 (1'b1 in each defined bit) RW
0x608 RETRANSMIT_XOFF_HOLDOFF_QUANTA [15:0] Specifies hold-off time from XOFF pause frame transmission until retransmission, if retransmission hold-off functionality is enabled and pause request remains at the value of 1. If your IP core implements priority-based flow control with multiple priority queues, this register provides access to an internal table of retransmit-hold-off times, one for each priority queue. Accesses are indexed by the value in the TX_PAUSE_QNUMBER register.

Unit is quanta. One quanta is 512 bit times, which varies according to the datapath width (256 or 512 depending on the IP core variation) and the clk_txmac frequency. Note that in the case of 100GbE IP cores, one quanta is effectively one clk_txmac clock cycle.

Pause request can be either of the TX_PAUSE_REQUEST register pause request bit and the pause_insert_tx signal.

0xFFFF RW
0x609 TX_PAUSE_QUANTA [15:0] Specifies the pause time to be included in XOFF frames.

If your IP core implements priority-based flow control with multiple priority queues, this register provides access to an internal table of pause times, one for each priority queue. Accesses are indexed by the value in the TX_PAUSE_QNUMBER register.

Unit is quanta. One quanta is 512 bit times, which varies according to the datapath width (256 or 512 depending on the IP core variation) and the clk_txmac frequency. In 100GbE IP cores, a quanta is effectively a single clk_txmac clock cycle.

0xFFFF RW
0x60A if you set the value of Flow control mode to Standard flow control in the LL 40-100GbE parameter editor. TX_XOF_EN [0]

Enable the TX MAC to pause outgoing Ethernet traffic in response to a pause frame received on the RX Ethernet link and forwarded to the TX MAC by the RX MAC.

If the cfg_enable bit of the RX_PAUSE_ENABLE register has the value of 1, the RX MAC processes incoming pause frames. When the RX MAC processes an incoming pause frame with an address match, it notifies the TX MAC to pause outgoing traffic on the TX Ethernet link. The TX MAC pauses outgoing traffic on the TX Ethernet link in response to this notification only if bit [0] of the TX_XOF_EN register has the value of 1.

The value in the TX_XOF_EN register is only relevant when the cfg_enable bit of the RX_PAUSE_ENABLE register has the value of 1. If the cfg_enable bit of the RX_PAUSE_ENABLE register has the value of 0, pause frames received on the RX Ethernet link do not reach the TX MAC.

1'b0 RW
0x60A if you set the value of Flow control mode to Priority-based flow control in the LL 40-100GbE parameter editor. TX_PAUSE_QNUMBER [2:0] Queue number (index to internal table) of queue whose relevant values are currently accessible (readable and writeable) in these registers:
  • RETRANSMIT_XOFF_HOLDOFF_QUANTA at offset 0x608
  • TX_PAUSE_QUANTA at offset 0x609
0 RW
0x60B CFG_RETRANSMIT_HOLDOFF_EN [0] The CFG_RETRANSMIT_HOLDOFF_EN and CFG_RETRANSMIT_HOLDOFF_QUANTA registers provide a mechanism to specify a uniform retransmission hold-off delay for all priority queues. If CFG_RETRANSMIT_HOLDOFF_EN has the value of 1, the IP core enforces a retransmission hold-off delay for each priority queue that is the longer of the queue-specific retransmission hold-off delay accessible in the RETRANSMIT_XOFF_HOLDOFF_QUANTA register (if enabled) and the retransmission hold-off delay specified in the CFG_RETRANSMIT_HOLDOFF_QUANTA register.

CFG_RETRANSMIT_HOLDOFF_QUANTA unit is quanta. One quanta is 512 bit times, which varies according to the datapath width (256 or 512 depending on the IP core variation) and the clk_txmac frequency. In 100GbE IP cores, a quanta is effectively a single clk_txmac clock cycle.

These registers are present only if you set the value of Flow control mode to Priority-based flow control in the LL 40-100GbE parameter editor.

1'b0 RW
0x60C CFG_RETRANSMIT_HOLDOFF_QUANTA [15:0]
0x60D TX_PFC_DADDRL [31:0]

TX_PFC_DADDRH contains the 16 most significant bits of the destination address for PFC pause frames.

TX_PFC_DADDRL contains the 32 least significant bits of the destination address for PFC pause frames.

This feature allows you to program a destination address other than the standard multicast address for PFC frames, for debug or proprietary purposes.

{TX_PFC_DADDRH[15:0],TX_PFC_DADDRL[31:0]} can be a broadcast, muilticast, or unicast address.

These registers are present only if you set the value of Flow control mode to Priority-based flow control in the LL 40-100GbE parameter editor.

0xC200_0001 RW
0x60E TX_PFC_DADDRH [15:0] 0x0180 RW
0x60F TX_PFC_SADDRL [31:0]

TX_PFC_SADDRH contains the 16 most significant bits of the source address for PFC pause frames.

TX_PFC_SADDRL contains the 32 least significant bits of the source address for PFC pause frames.

These registers are present only if you set the value of Flow control mode to Priority-based flow control in the LL 40-100GbE parameter editor.

0xCBFC_5ADD RW
0x610 TX_PFC_SADDRH [15:0] 0xE100 RW
Table 43.  RX Ethernet Flow Control (Pause Functionality) Registers Some registers are different depending on whether you select Standard flow control or Priority-based flow control in the Low Latency 40-100GbE parameter editor. Where the difference is only whether the register refers to the single standard flow control priority class or whether distinct bits in the register refer to the individual priority queues, the two uses are documented together. In that case we understand that standard flow control effectively supports a single priority queue.

Addr

Name

Bit

Description

HW Reset Value

Access

0x700 RXSFC_REVID [31:0] RX standard flow control module revision ID. 0x01282014 RO
0x701 RXSFC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x702 RXSFC_NAME_0 [31:0] First 4 characters of IP core variation identifier string "40gSFCRxCSR" or "100gSFCRxCSR". RO
0x703 RXSFC_NAME_1 [31:0] Next 4 characters of IP core variation identifier string "40gSFCRxCSR" or "100gSFCRxCSR". RO
0x704 RXSFC_NAME_2 [31:0] Final 4 characters of IP core variation identifier string "40gSFCRxCSR" or "100gSFCRxCSR". RO

0x705

RX_PAUSE_ENABLE [N-1:0]

cfg_enable bits. When bit [n] has the value of 1, the RX MAC processes the incoming pause frames for priority class n whose address matches {DADDR1[31:0],DADDR0[15:0]}. When bit [n] has the value of 0, the RX MAC does not process any incoming pause frames for priority class n.

When the RX MAC processes an incoming pause frame with an address match, it notifies the TX MAC to pause outgoing traffic on the TX Ethernet link. If you implement priority-based flow control, the TX MAC pauses outgoing traffic from the indicated priority queue to the TX Ethernet link in response to this notification. If you implement standard flow control, the TX MAC pauses outgoing traffic on the TX Ethernet link in response to this notification only if bit [0] of the TX_XOF_EN register has the value of 1.

N'b1...1 (1'b1 in each defined bit) RW

0x706

RX_PAUSE_FWD [0] cfg_fwd_ctrl bit. When this bit has the value of 1, the RX MAC forwards matching pause frames to the RX client interface. When this bit has the value of 0, the RX MAC does not forward matching pause frames to the RX client interface. In both cases, the RX MAC forwards non-matching pause frames to the RX client interface. 1'b0 RW

0x707

RX_PAUSE_DADDRL

[31:0]

RX_PAUSE_DADDRL contains the 32 least significant bits of the destination address for pause frame matching.

RX_PAUSE_DADDRH contains the 16 most significant bits of the destination address for pause frame matching.

When pause frame processing is turned on, if {RX_PAUSE_DADDRH[15:0],RX_PAUSE_DADDRL[31:0]} matches the incoming pause frame destination address, the IP core processes the pause frame. if there is no match, the IP core does not process the pause frame.

{RX_PAUSE_DADDRH[15:0],RX_PAUSE_DADDRL[31:0]} can be a broadcast, muilticast, or unicast address.

0xC200_0001

RW

0x708

RX_PAUSE_DADDRH

[15:0]

0x0180

RW

Related Information
9 N is the number of priority queues. If the IP core implements Ethernet standard flow control, N is 1.
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