Visible to Intel only — GUID: nik1411172552594
Ixiasoft
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices
2.2. Licensing IP Cores
2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. Low Latency 40-100GbE IP Core Testbenches
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches
2.10. Compiling the Full Design and Programming the FPGA
2.11. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.5. Clock Requirements for 40GBASE-KR4 Variations
2.7.6. External TX MAC PLL
2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.9.1. Generating the Low Latency 40-100GbE Testbench
2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches
2.9.3. Simulating with the Modelsim Simulator
2.9.4. Simulating with the NCSim Simulator
2.9.5. Simulating with the VCS Simulator
2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3.2.1. Low Latency 40-100GbE IP Core TX Datapath
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces
3.2.3. Low Latency 40-100GbE IP Core RX Datapath
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface
3.2.5. Low Latency 100GbE CAUI–4 PHY
3.2.6. External Reconfiguration Controller
3.2.7. External Transceiver PLL
3.2.8. External TX MAC PLL
3.2.9. Congestion and Flow Control Using Pause Frames
3.2.10. Pause Control and Generation Interface
3.2.11. Pause Control Frame Filtering
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. 1588 Precision Time Protocol Interfaces
3.2.15. PHY Status Interface
3.2.16. Transceiver PHY Serial Data Interface
3.2.17. Low Latency 40GBASE-KR4 IP Core Variations
3.2.18. Control and Status Interface
3.2.19. Arria 10 Transceiver Reconfiguration Interface
3.2.20. Clocks
3.2.21. Resets
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus
3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering
3.2.3.2. 40-100GbE IP Core Preamble Processing
3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. 40-100GbE IP Core CRC Checking
3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling
3.2.3.6. RX CRC Forwarding
3.2.3.7. Inter-Packet Gap
3.2.3.8. Pause Ignore
3.2.3.9. Control Frame Identification
Visible to Intel only — GUID: nik1411172552594
Ixiasoft
1.3.3. Hardware Testing
Altera performs hardware testing of the key functions of the Low Latency 40-100GbE MAC and PHY IP core using standard 40-100Gbps Ethernet network test equipment and optical modules. The Altera hardware tests of the Low Latency 40‑100GbE IP core also ensure reliable solution coverage for hardware related areas such as performance, link synchronization, and reset recovery. The IP core is tested with Stratix V devices.