Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Public
Document Table of Contents

1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores

Resource utilization changes depending on the parameter settings you specify in the Low Latency 40-100GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the LL 40-100GbE parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 6.  IP Core FPGA Resource Utilization in Arria 10 Devices Lists the resources and expected performance for selected variations of the Low Latency 40-100GbE IP cores in an Arria 10 device.

These results were obtained using the Quartus II v14.1 software.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.

40GbE Variation

ALMs

Dedicated Logic Registers

Memory

M20K

40GbE variation A

5400 12800 13

40GbE variation B

10100 21200 13
40GbE variation C 11000 24100 13

40GbE variation D

14200 31100 17

40GbE variation E

14400 28200 26
40GbE variation F 16300 29300 26

100GbE Variation

ALMs

Dedicated Logic Registers

Memory

M20K

100GbE variation A

13100 29000 29

100GbE variation B

21200 47600 61
100GbE variation C 22500 51800 61

100GbE variation D

27000 63200 65

CAUI-4 Variation

ALMs

Dedicated Logic Registers

Memory

M20K

CAUI-4 variation B

22700 51300 61