AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.4. Soft PCS Latency

Because the designs for the soft PCS and the hard PCS are different, their latencies are different. The extra flip-flops that are added to the soft PCS datapath to meet the tight timing requirements increase the overall soft PCS latency.

Table 2.   Soft PCS LatencyThe table shows the latencies measured in number of usr_clk signal clock cycles for various blocks in the soft PCS datapath.

Data width conversion

TX reg

TX data width adapter

8b/10b encoder

TX bit slip

TX Phase measuring FIFO

RX reg

word aligner

RX Phase measuring FIFO

8b10b decoder

RX data width adapter

32 -> 80

1

4 or 51

2

2

(1+tx_fifo_latency)*2

1

10

(1+rx_fifo_latency)*2

2

4

32 -> 20

1

2

0.5

1

(1+tx_fifo_latency)/2

1

2.5

(1+rx_fifo_latency)/2

0.5

2.5 or 2 2

1 Latency of 5 usr-clk cycles for BChex (control character K28.5) at lower word and 4 usr_clk cycles for BC hex at upper word.
2 Latency of 2.5 usr-clk cycles for BChex (control character K28.5) at lower word and 2 usr_clk cycles for BC hex at upper word.
Level Two Title