AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.1. Native PHY IP Settings in PMA Direct Mode

The following figures show the Native PHY IP settings to implement a duplex transceiver channel in PMA direct mode. For this example, the reference clock frequency is set to 491.52 MHz. You can change the reference clock frequency using the drop down menu.

Figure 1. Datapath Options, TX PMA and TX PLL Settings


Figure 2. RX PMA Settings


In this example, only one TX PLL is used to drive the channels.

The Native PHY IP does not include an embedded reset controller. You can either design custom reset logic or incorporate Altera’s “Transceiver PHY Reset Controller IP Core” to implement reset functionality.

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