1.3. Soft PCS Clocking
Two system clocks are provided from the core to the soft PCS, unlike the hard PCS where the clock from the transceiver is sent to the core. The upper layer clock usr_clk is used to clock the 32 bit data. The usr_pma_clk is used to clock the 80 bit or 20 bit data. These two clocks are generated from the user system clock.
| Data Rate (Gbps) |
Base Data Rate (Gbps) |
Local Clock Divider Factor |
usr_clk (MHz) |
usr_pma_clk (MHz) |
Core to Soft PCS Data Width |
PMA Width |
|---|---|---|---|---|---|---|
| 9.8304 |
9.8304 |
1 |
245.76 |
122.88 |
32 |
80 |
| 6.144 |
6.144 |
1 |
153.6 |
76.8 |
32 |
80 |
| 4.9152 |
9.8304 |
2 |
122.88 |
61.44 |
32 |
80 |
| 3.072 |
6.144 |
2 |
76.8 |
153.6 |
32 |
20 |
| 2.4576 |
9.8304 |
4 |
61.44 |
122.88 |
32 |
20 |
| 1.2288 |
9.8304 |
8 |
30.72 |
61.44 |
32 |
20 |
Both the usr_clk and usr_pma_clk must have 0 parts per million (ppm) phase difference to avoid timing violations in the TX and RX data width adapter blocks. To ensure 0 ppm phase difference between both the clock domains, generate the usr_clk and usr_pma_clk internally using the fPLL from the reference clock source.
You may choose to generate both clocks from an external PLL; however, ensure that the skew between these two clocks is minimized on the PCB. You can select the pin assignments such that dedicated clock pins are used for both clocks. Use the QSF assignments below if you want to use the dedicated clock pins.
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to usr_clk
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to usr_pma_clk