AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.5. Auto Rate Negotiation

In Arria V GT and Arria V ST FPGAs, a soft PCS implementation supports auto rate negotiation from 9.8304 Gbps to 1.2288 Gbps. Altera recommends to use the hard PCS for CPRI interfaces where the maximum interface data rate is 6.144 Gbps or lower. In this example, the channels are initialized at the highest supported data rate and are switched to successive lower data rates.

Figure 5. Design Block Diagram for Auto Rate Negotiation from 9.8304 Gbps to Lower Data RatesThe following figure shows an example design of auto rate negotiation for 1.2G /2.5G /3.1G /4.9G/ 6.1G/ 9.8G.

Section Content
CMU PLL Optimization
Configurations
Steps for Auto Rate Negotiation

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