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1. Intel® Stratix® 10 ADC Overview
2. Intel® Stratix® 10 ADC Architecture and Features
3. Intel® Stratix® 10 ADC Design Considerations
4. Intel® Stratix® 10 ADC Implementation Guides
5. Intel® Stratix® 10 ADC IP Core References
6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide
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4. Intel® Stratix® 10 ADC Implementation Guides
The Voltage Sensor and Temperature Sensor IP cores are soft controllers for the ADC hard IP blocks. With these IP cores, you can read sampling values from the different ADC channels through the SDM.
- To sample external or internal voltages, use the Voltage Sensor Intel® FPGA IP.
- To sample the on-die temperature using the internal TSDs, use the Temperature Sensor Intel® FPGA IP.
The Voltage Sensor or Temperature Sensor IP core does not have configurable options in the Intel® Quartus® Prime parameter editor. To use the IP core, instantiate an instance of it in your design and use the digital signal interface of the IP core to access the voltage or temperature readouts.
The command and response interfaces of the Voltage Sensor and Temperature Sensor IP cores are Avalon® Streaming (Avalon-ST) interfaces with ready latency of 0.
Note: You cannot simulate the Voltage Sensor and Temperature Sensor IP cores because the IP cores receive the sampling values through the SDM. To validate these IP cores, Intel recommends hardware evaluation.