Intel® Stratix® 10 Analog to Digital Converter User Guide

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ID 683612
Date 2/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 ADC Overview 2. Intel® Stratix® 10 ADC Architecture and Features 3. Intel® Stratix® 10 ADC Design Considerations 4. Intel® Stratix® 10 ADC Implementation Guides 5. Intel® Stratix® 10 ADC IP Core References 6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide
1. Intel® Stratix® 10 ADC Overview x
1.1. Release Information for Voltage Sensor and Temperature Sensor Intel® FPGA IP Cores
2. Intel® Stratix® 10 ADC Architecture and Features x
2.1. Intel® Stratix® 10 Voltage Sensor 2.2. Intel® Stratix® 10 Temperature Sensing Diodes
2.1. Intel® Stratix® 10 Voltage Sensor x
2.1.1. Voltage Conversion
2.2. Intel® Stratix® 10 Temperature Sensing Diodes x
2.2.1. Internal Temperature Sensor 2.2.2. External Temperature Sensor 2.2.3. Temperature Sensor Channels and Locations 2.2.4. Temperature Sensor Error Codes
2.2.1. Internal Temperature Sensor x
2.2.1.1. Temperature Calculation for the Internal Temperature Sensor
3. Intel® Stratix® 10 ADC Design Considerations x
3.1. Guidelines: Selecting Temperature Sensing Chip to Interface with the Intel® Stratix® 10 External TSD 3.2. Guidelines: Using External Temperature Sensors 3.3. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel® Stratix® 10 External TSD
4. Intel® Stratix® 10 ADC Implementation Guides x
4.1. Sampling the Intel® Stratix® 10 Voltage Sensor Channels 4.2. Reading the Intel® Stratix® 10 Internal Temperature Sensing Diodes
5. Intel® Stratix® 10 ADC IP Core References x
5.1. Voltage Sensor Intel® FPGA IP Digital Signals 5.2. Temperature Sensor Intel® FPGA IP Digital Signals
1. Intel® Stratix® 10 ADC Overview
2. Intel® Stratix® 10 ADC Architecture and Features
3. Intel® Stratix® 10 ADC Design Considerations
4. Intel® Stratix® 10 ADC Implementation Guides
5. Intel® Stratix® 10 ADC IP Core References
6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide

5.1. Voltage Sensor Intel® FPGA IP Digital Signals

These signals are the operational signals of the Voltage Sensor IP core. The command and response interfaces are Avalon® Streaming (Avalon-ST) interfaces with ready latency of 0.
Figure 8.  Voltage Sensor IP Core


Table 5.  Clock and Reset Signals
Signal

Width

(Bit)

 Type Description
clk 1 Input All signals in the IP core is synchronous to this clock. The frequency supported for this clock is from 10 MHz to 100 MHz.
reset 1 Input Active high reset. Deassert this signal synchronous to the clock.
Table 6.  Command Signals
Signal

Width

(Bit)

 Type Description
cmd_valid 1

Input

Assert this signal high to send voltage sampling request to the IP core.

cmd_ready 1

Output

The IP core drives this signal high to indicate that the IP core is ready to receive command.

cmd_data 16

Input

Bitmask to indicate from which channel to return the voltage value. Send this data signal together with the cmd_valid signal.

  • Bit 0 to 1—sample the external voltage values from the specified analog input channels.
  • Bits 2 to 15—sample the internal voltage values from the specified channels.

For example, 0000001000010001 signals the IP core to sample the voltage values from channels 0, 4, and 9.

Set only valid bits in the cmd_data word. Otherwise, the response from the voltage sensor is undefined.

Table 7.  Response Signals
Signal

Width

(Bit)

 Type Description
rsp_valid 1

Output

Indication from the IP core that the voltage value is ready.

rsp_channel 4

Output

Indicates the channel of the voltage value sampled from the analog inputs or internal supplies.

rsp_data 32

Output

The voltage value in a signed 32-bit fixed-point binary format, with 16 bits below the binary point.

rsp_startofpacket 1

Output

Indicates that the current transfer is the start of packet.

rsp_endofpacket 1 Output Indicates that the current transfer is the end of packet.
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