Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.1.3. Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP

The Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP inserts a register stage in the Avalon® memory mapped command and response paths. The bridge accepts commands on its agent port and propagates the commands to its host port. The pipeline bridge provides separate parameters to turn on pipelining for command and response signals.
Note: The Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP has a readLatency of 0 and readdatavalid of 1. Therefore, the bridge does not support fixed-latency pipelined read transfers.

The Maximum pending read transactions parameter is the maximum number of pending reads that the Avalon® Memory Mapped bridge can queue up. To determine the best value for this parameter, review this same option for the bridge's connected agents and identify the highest value of the parameter, and then add the internal buffering requirements of the Avalon® Memory Mapped bridge. In general, the value is between 4 and 32. The limit for maximum queued transactions is 64.

You can use the Avalon® Memory Mapped bridge to export a single Avalon® memory mapped agent interface to control multiple Avalon® memory mapped agent devices. The pipelining feature is optional.

Figure 245.  Avalon® Memory Mapped Pipeline Bridge IP and XAUI PHY Transceiver IPIn this example, the bridge transfers commands received on its agent interface to its host port.

Because the agent interface is exported to the pins of the device, having a single agent port, rather than separate ports for each agent device, reduces the pin count of the FPGA. Refer to Interconnect Pipelining for more information.