2.9.1. Interconnect Parameters

Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

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Date 10/02/2023

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2.9.1. Interconnect Parameters

The following parameters are available on the Domains tab:

Table 14. Interconnect Parameters
Option	Description
Enable all pipeline stages	FALSE—default setting. The Limit interconnect pipeline stages to value and post-adaptation assignments control pipeline insertion. TRUE—enables all pipeline stages within this domain. Ignores the Limit interconnect pipeline stages to and any post-adaptation assignment. Also disables manual editing of pipelines in the schematic. Although this setting ignores post-adaptation assignments, the assignments still remain in the design.
Limit interconnect pipeline stages to	Specifies the maximum number of pipeline stages that Platform Designer can insert in each command and response path to increase the f_MAX at the expense of additional latency. You can specify between 0 and 4 as the maximum number of pipeline stages to insert. The default value is 1. A value of 0 indicates no pipelines and a combinational datapath. When you specify 1 or greater, Platform Designer inserts up to the number you specify, depending on availability of pipeline locations. Note: If certain adapters or IP components are not present in the interconnect, or if there are not enough pipelineable locations in the interconnect, Platform Designer does not add all of the pipeline stages specified. Click Show System with Interconnect to view the number of stages added for a particular domain.
Clock crossing adapter type	Specifies the default implementation for automatically inserted clock crossing adapters: Handshake—this adapter uses a simple handshaking protocol to propagate transfer control signals and responses across the clock boundary. This methodology uses fewer hardware resources because each transfer is safely propagated to the target domain before the next transfer can begin. The Handshake adapter is appropriate for systems with low throughput requirements. FIFO—this adapter uses dual-clock FIFOs for synchronization. The latency of the FIFO-based adapter is a couple of clock cycles more than the handshaking clock crossing component. However, the FIFO-based adapter can sustain higher throughput because it supports multiple transactions at any given time. FIFO-based clock crossing adapters require more resources. The FIFO adapter is appropriate for memory-mapped transfers requiring high throughput across clock domains. Auto—if you select Auto, Platform Designer specifies the FIFO adapter for bursting links, and the Handshake adapter for all other links.
Automate default slave insertion	Directs Platform Designer to automatically insert a default Avalon agent or AXI subordinate for undefined memory region accesses during system generation.¹
Enable instrumentation	When you set this option to TRUE, Platform Designer enables debug instrumentation in the Platform Designer interconnect, which then monitors interconnect performance in the system console.
Interconnect reset source	Select Default or a specific reset signal in your design.
Burst adapter implementation	Allows you to choose the converter type that Platform Designer applies to each burst. Generic converter (slower, lower area)—default setting. Controls all burst conversions with a single converter that is able to adapt incoming burst types. This results in an adapter that has lower f_MAX, but smaller area. Per-burst-type converter (faster, higher area)—controls incoming bursts with a particular converter, depending on the burst type. This results in an adapter that has higher f_MAX, but higher area. This setting is useful when you have AXI managers or subordinates and you want a higher f_MAX.
Width adapter implementation	Generic converter (slower, lower area)—default. Controls all width adaptations with a single converter that is able to adapt incoming widths. This results in an adapter that has lower f_MAX, but smaller area. Optimized converter (faster, higher area)—controls width adaptations with a particular converter, depending on the width. This results in an adapter that has higher f_MAX, but higher area. This setting is useful when you have AXI managers or subordinates and you want a higher f_MAX.
Enable ECC protection	Specifies the default implementation for ECC protection for memory elements. FALSE—default. Disables ECC protection for memory elements in the Platform Designer interconnect. TRUE—enables ECC protection for memory elements. Platform Designer interconnect sends uncorrectable errors arising from memory as `DECODEERROR` (`DECERR`) on the Avalon® response bus. For more information about Error Correction Coding (ECC), refer to Error Correction Coding (ECC) in Platform Designer Interconnect.
Use synchronous reset	When set to TRUE, all registers in the interconnect use synchronous reset. Assert the reset for at least 16 cycles and start transactions 16 cycles after deassertion of the reset. This period allows all the IP components to reset and come out of the reset state. To avoid deadlocks in the interconnect, reset hosts and agents simultaneously. If hosts and agents have different resets, agents must reset only after responding to all necessary transactions. The Use synchronous reset option is enabled by default for Intel® Hyperflex™ architecture devices, but is disabled by default for all other devices. Enabling synchronous reset for the interconnect does not enable synchronous reset for IP components in the system. You must separately enable the synchronous reset parameter for any component.
Optimize size for Avalon Response Data Fifo	When enabled, Platform Designer does not increase the size of the Avalon® interface agent read FIFO to the next power of 2. You can enable this setting to decrease the size of the FIFO if needed.
Response FIFO Type	Specifies the implementation method for the Platform Designer response FIFO that stores information for processing of response in the interconnect, such as width adaptation and routing to the Avalon® host or AXI manager. The following options are available: Register Based—default option that implements the response FIFO using registers. When Register Based is selected, FIFO uses the LUT’s to hold responses. This consumes more LUT’s, but the minimum response latency is 1. Embedded Memory Based—implements the response FIFO using M20K memory blocks, rather than LUTs. When you specify Embedded Memory Based, the minimum response latency is 3, and FIFO consumes far fewer LUT resources, but consumes M20K memory resources.

¹ This document now refers to the Avalon® "host" and "agent," and the AXI "manager" and "subordinate," to replace former terms. Refer to the current AMBA AXI and ACE Protocol Specification for the latest AMBA AXI and ACE protocol terminology.

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Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

2.9.1. Interconnect Parameters