Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/02/2023
Public

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7.4.3.3.2. Avalon® Data Pattern Generator IP Command Registers

Table 141.   Avalon® Data Pattern Generator IP Command Register MapShows the offset for the command registers. Each register is 32-bits wide.
Offset Register Name
base + 0 cmd_lo
base + 1 cmd_hi

The cmd_lo is pushed into the FIFO only when the cmd_lo register is addressed.

Table 142.   cmd_lo Register Bits
Bits Name Access Description
[15:0] SIZE RW The segment size in symbols. Except for the last segment in a packet, the size of all segments must be a multiple of the configured number of symbols per beat. If this condition is not met, the Data Pattern Generator IP inserts additional symbols to the segment to ensure the condition is fulfilled.
[29:16] CHANNEL RW The channel to send the segment on. If the channel signal is less than 14 bits wide, the Data Pattern Generator IP uses the low order bits of this register to drive the signal.
[30] SOP RW Set this bit to 1 when sending the first segment in a packet. This bit is ignored when data packets are not supported.
[31] EOP RW Set this bit to 1 when sending the last segment in a packet. This bit is ignored when data packets are not supported.
Table 143.   cmd_hi Register Bits
Bits Name Access Description
[15:0] SIGNALED ERROR RW Specifies the value to drive the error signal. A non-zero value creates a signaled error.
[23:16] DATA ERROR RW The output data is XORed with the contents of this register to create data errors. To stop creating data errors, set this register to 0.
[24] SUPPRESS SOP RW Set this bit to 1 to suppress the assertion of the startofpacket signal when the first segment in a packet is sent.
[25] SUPRESS EOP RW Set this bit to 1 to suppress the assertion of the endofpacket signal when the last segment in a packet is sent.