Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/02/2023
Public

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6.10.9.2. Adjacent Bytelanes with Partial Width Transactions

The following limitations apply to Avalon® to AXI partial width transactions with use of adjacent bytelanes:
  • Avalon® interfaces only support adjacent bytelanes if the interface requires more than one byte enable. For example: 1100, 0011.
  • AXI fully supports use of bytelanes that are not adjacent. For example: 1010, 0101.