Intel® Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 12/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
1. Intel® Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Intel® Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP Core
2.3.1. Advanced SEU Detection IP Core x
2.3.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Intel® Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Error Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI
4.9. Intel® Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection Intel® FPGA IP References x
5.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.2. Advanced SEU Detection IP Core Ports
6. Intel® Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

2.3.1.4.1. SMH Revision 4 File Format

Table 5.  SMH Revision 4 File Format for Intel® Stratix® 10 Devices
Block Sub - block 32-bit Word Bit Description
Sensitivity map header — 0 [31:0] Identification word for SMH format and its version, 0xXE445341.
1 [31:8] Reserved
[7:0] ASD Region bitmask size. ASD region bitmask size is the upper bound power of 2 for maximal ASD Region ID in design, can be 1,2,4,8,16 or 32.
2 [31:0] Address of the Sector Information block.
Sectors Information block Sector 0 Information 0 [31:0] Address of the sector 0 encoding scheme.
1 [31:0] Address of the encoded sector 0 sensitivity data.
2 [23:8] The number of ASD region bitmasks used by sector 0 (i.e. number of SMH tags). Value of 0 indicates that there are no sensitive bits in a sector.
[7:0] The sector 0 SMH tag size in bits, can be 1, 2, 4, 8.
… … … …
Sector N Information N*3 .. N*3+2 … …
Sectors Encoding block Sector Encoding 0 0 [31:16] Identification word 0xEEEE
[15:0] Size of a single frame encoding (i.e. bit->tag index) map in bytes.
1 [31:0] Address of the frame information (FADD).
2 [31:0] Address of the frame encoding map (EADD).
FADD [31:20] Index of encoding map for frame 0
[19:0] Sensitivity data offset into sector sensitivity data for frame 0.
… … …
FAAD+K [31:20] Index of encoding map for last frame
[19:0] Sensitivity data offset into sector sensitivity data for last frame.
EADD

Frame encoding map 0. Contains the mapping of ‘bit position’ in frame to 16-bit ‘bit group sensitivity tag index’ into frame sensitivity data.

For all the phantom bits in a frame ‘bit group sensitivity index’ is set to 0xFFFF since no sensitivity data is needed.
… … …
… … … …
Sector Encoding M ...
Sectors Sensitivity Data Sector 0 Data 0 [31:16] Sector data identification word (0xDDDD)
[15:0] Reserved
1..L  

Sector Regions Map:

L = ('ASD region bitmask size' * 'number of ASD region masks for sector'+31)/32
L+1

Encoded frames sensitivity data. Data for each frame is located at:

offset = L+1+frame sensitivity data offset * sector SMH tag size
… … … …
Sector N Data …
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