Intel® MAX® 10 Analog to Digital Converter User Guide

Download PDF
ID 683596
Date 1/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Analog to Digital Converter Overview 2. Intel® MAX® 10 ADC Architecture and Features 3. Intel® MAX® 10 ADC Design Considerations 4. Intel® MAX® 10 ADC Implementation Guides 5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References 6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
1. Intel® MAX® 10 Analog to Digital Converter Overview x
1.1. ADC Block Counts in Intel® MAX® 10 Devices 1.2. ADC Channel Counts in Intel® MAX® 10 Devices 1.3. Intel® MAX® 10 ADC Vertical Migration Support 1.4. Intel® MAX® 10 Single or Dual Supply Devices 1.5. Intel® MAX® 10 ADC Conversion
1.5. Intel® MAX® 10 ADC Conversion x
1.5.1. Voltage Representation Conversion
2. Intel® MAX® 10 ADC Architecture and Features x
2.1. Intel® MAX® 10 ADC Hard IP Block 2.2. Modular ADC Core and Modular Dual ADC Core IP Cores 2.3. Intel FPGA ADC HAL Driver 2.4. ADC Toolkit for Testing ADC Performance 2.5. ADC Logic Simulation Output
2.1. Intel® MAX® 10 ADC Hard IP Block x
2.1.1. ADC Block Locations 2.1.2. Single or Dual ADC Devices 2.1.3. ADC Analog Input Pins 2.1.4. ADC Prescaler 2.1.5. ADC Clock Sources 2.1.6. ADC Voltage Reference 2.1.7. ADC Temperature Sensing Diode 2.1.8. ADC Sequencer 2.1.9. ADC Timing
2.1.7. ADC Temperature Sensing Diode x
2.1.7.1. Temperature Measurement Code Conversion 2.1.7.2. Temperature Measurement Sampling Rate
2.1.8. ADC Sequencer x
2.1.8.1. Guidelines: ADC Sequencer in Modular Dual ADC Core IP Core
2.2. Modular ADC Core and Modular Dual ADC Core IP Cores x
2.2.1. Modular ADC Core IP Core Configuration Variants 2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
2.2.1. Modular ADC Core IP Core Configuration Variants x
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage 2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection 2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage 2.2.1.4. Configuration 4: ADC Control Core Only
2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture x
2.2.2.1. ADC Control Core 2.2.2.2. Sequencer Core 2.2.2.3. Sample Storage Core 2.2.2.4. Response Merge Core 2.2.2.5. Dual ADC Synchronizer Core 2.2.2.6. Threshold Detection Core
2.5. ADC Logic Simulation Output x
2.5.1. Fixed ADC Logic Simulation Output 2.5.2. User-Specified ADC Logic Simulation Output
3. Intel® MAX® 10 ADC Design Considerations x
3.1. Guidelines: ADC Ground Plane Connection 3.2. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 3.3. Guidelines: Board Design for Analog Input 3.4. Guidelines: Board Design for ADC Reference Voltage Pin
4. Intel® MAX® 10 ADC Implementation Guides x
4.1. Creating Intel® MAX® 10 ADC Design 4.2. Customizing and Generating Modular ADC Core IP Core 4.3. Parameters Settings for Generating ALTPLL IP Core 4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core 4.5. Completing ADC Design
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References x
5.1. Modular ADC Core Parameters Settings 5.2. Modular Dual ADC Core Parameters Settings 5.3. Valid ADC Sample Rate and Input Clock Combination 5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals 5.5. Modular ADC Core Register Definitions 5.6. ADC HAL Device Driver for Nios® Processor
5.1. Modular ADC Core Parameters Settings x
5.1.1. Modular ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.2. Modular Dual ADC Core Parameters Settings x
5.2.1. Modular Dual ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals x
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core 5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core 5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core 5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core 5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core 5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core 5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.5. Modular ADC Core Register Definitions x
5.5.1. Sequencer Core Registers 5.5.2. Sample Storage Core Registers
5.6. ADC HAL Device Driver for Nios® Processor x
5.6.1. Driver API
1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide

4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core

Navigate through the Modular ADC Core IP core parameter editor and specify the settings required for your design. After you have specified all options as listed in the following tables, you can generate the HDL files and the optional simulation files.
Note: The Modular ADC Core and Modular Dual ADC Core IP cores support generating only Verilog* simulation scripts.

Intel recommends that you save the generated files in the design file directory (default setting).

For more information about each Modular ADC Core or Modular Dual ADC Core parameter, refer to the related information section.

Table 13.  Parameter Settings in General Group
Parameter Setting
Core Variant

There are four configuration variants of the Modular ADC Core IP core. Select the core variant that meets your requirement. For more information, refer to the related information.

Debug Path

Turn this on to enable the debug path for the selected core variant. You can use the ADC Toolkit to monitor the ADC performance.
Generate IP for which ADCs of this device?

For devices with two ADC blocks, select the ADC block for which you are generating the IP core. There are feature differences between the two ADC blocks. The temperature sensor is available only in the first ADC block. There are also different channel counts in both ADC blocks.

ADC Sample Rate

Select the predefined sampling rate for the ADC from 25 kHz to 1 MHz. A lower sampling rate allows you greater flexibility in designing your ADC front end driver circuit. For example, using a lower sampling rate gives you a wider settling time margin for your filter design.

The sampling rate you select affects which ADC input clock frequencies are available.

Refer to the related information for more details about the sampling rate and the required settling time.

ADC Input Clock

Select the same frequency that you set for the ALTPLL IP core that clocks the Modular ADC Core IP core. When configuring the ALTPLL IP core, specify a clock frequency that is supported by the ADC sampling rate. For more details, refer to the related information.

Reference Voltage Source

Select whether you want to use external or internal reference voltage.

There is only one VREF pin. For dual ADC blocks, you can use one external VREF source for both ADC blocks, or external VREF for one ADC block and internal VREF for the other ADC block.

External Reference Voltage

If you use external VREF source in your design, specify the VREF level.

Enable user created expected output file If you want to use your own stimulus input file to simulate the ADC output data, enable this function and specify the file for the specific ADC channel. For more information about user-specified ADC logic simulation output, refer to the related information.
Table 14.  Parameters Settings in Channels GroupYou can navigate through the tabs for all the available channels and turn on the channel you want to use. In each channel (and TSD) tab, you can specify the settings in this table.
Parameter Setting
Use Channel 0 (Dedicated analog input pin - ANAIN)

This option is available in the CH0 tab.

CH0 is the dedicated analog input channel. If you want to use the dedicated analog input, turn on this option.
User created expected output file

If you enabled the option to use your own stimulus input file to simulate the output data, click Browse and select the file for each enabled channel.

This option is available in all channel tabs except the TSD tab.
Use Channel N

You can select which dual-function ADC channels to turn on or off. There are 16 channels (CH1 to CH16) for single ADC devices and 8 channels (CH1 to CH8) for each ADC block in dual ADC devices.

Use on-chip TSD

This option is available in the TSD tab. The TSD channel is the temperature sensing channel.

Turn on this option if you want the IP core to read the built-in temperature sensor in the ADC block.

The sampling rate of the ADC block reduces to 50 kHz when it reads the temperature measurement. After it completes the temperature reading, the ADC sampling rate returns to 1 MHz.

For the Modular Dual ADC Core IP core, if you specify the TSD in a sequencer slot for ADC1, specify NULL in the same sequencer slot number for ADC2.

Enable Maximum threshold for Channel N

Turn on this option if you want to set a maximum threshold value for the channel.
Enter Maximum Threshold for Channel N

Enter the maximum threshold voltage for the channel. The IP core generates a threshold violation notification signal to indicate that the sampled data is over the threshold value that you specify.

Enable Maximum threshold for on-chip TSD (TSD tab)

Enter the maximum threshold temperature for the temperature sensor in Celsius. The IP core generates a threshold violation notification signal to indicate that the sampled temperature is over the temperature that you specify.

Enable Minimum threshold for Channel N

Turn on this option if you want to set a minimum threshold value for the channel.
Enter Minimum Threshold for Channel N

Enter the minimum threshold voltage for the channel. The IP core generates a threshold violation notification signal to indicate that the sampled data is below the threshold value that you specify.

Enter Minimum Threshold for on-chip TSD (TSD tab)

Enter the maximum threshold temperature for the temperature sensor in Celsius. The IP core generates a threshold violation notification signal to indicate that the sampled temperature is below the temperature that you specify.

Table 15.  Parameters Settings in Sequencer Group
Parameter Setting
Number of slot used

Select the number of channels to use for conversion. The parameter editor displays the number of slots available in the Conversion Sequence Channels based on your selection.

Slot N

For each available slot, select the channel to sample in the sequence. The available channels depend on the channels that you turned on in the Channels parameters group.

If you turned on a channel but do not select the channel in any of the sequencer slots, the unselected channel is not measured during the ADC sampling sequence.

The ADC block samples the measurements in the sequence you specify. After it reaches the last slot in the sequence, it repeats the sampling from the first slot.

Related Information
Level Two Title