Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 1/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Analog to Digital Converter Overview 2. Intel® MAX® 10 ADC Architecture and Features 3. Intel® MAX® 10 ADC Design Considerations 4. Intel® MAX® 10 ADC Implementation Guides 5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References 6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
1. Intel® MAX® 10 Analog to Digital Converter Overview x
1.1. ADC Block Counts in Intel® MAX® 10 Devices 1.2. ADC Channel Counts in Intel® MAX® 10 Devices 1.3. Intel® MAX® 10 ADC Vertical Migration Support 1.4. Intel® MAX® 10 Single or Dual Supply Devices 1.5. Intel® MAX® 10 ADC Conversion
1.5. Intel® MAX® 10 ADC Conversion x
1.5.1. Voltage Representation Conversion
2. Intel® MAX® 10 ADC Architecture and Features x
2.1. Intel® MAX® 10 ADC Hard IP Block 2.2. Modular ADC Core and Modular Dual ADC Core IP Cores 2.3. Intel FPGA ADC HAL Driver 2.4. ADC Toolkit for Testing ADC Performance 2.5. ADC Logic Simulation Output
2.1. Intel® MAX® 10 ADC Hard IP Block x
2.1.1. ADC Block Locations 2.1.2. Single or Dual ADC Devices 2.1.3. ADC Analog Input Pins 2.1.4. ADC Prescaler 2.1.5. ADC Clock Sources 2.1.6. ADC Voltage Reference 2.1.7. ADC Temperature Sensing Diode 2.1.8. ADC Sequencer 2.1.9. ADC Timing
2.1.7. ADC Temperature Sensing Diode x
2.1.7.1. Temperature Measurement Code Conversion 2.1.7.2. Temperature Measurement Sampling Rate
2.1.8. ADC Sequencer x
2.1.8.1. Guidelines: ADC Sequencer in Modular Dual ADC Core IP Core
2.2. Modular ADC Core and Modular Dual ADC Core IP Cores x
2.2.1. Modular ADC Core IP Core Configuration Variants 2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
2.2.1. Modular ADC Core IP Core Configuration Variants x
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage 2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection 2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage 2.2.1.4. Configuration 4: ADC Control Core Only
2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture x
2.2.2.1. ADC Control Core 2.2.2.2. Sequencer Core 2.2.2.3. Sample Storage Core 2.2.2.4. Response Merge Core 2.2.2.5. Dual ADC Synchronizer Core 2.2.2.6. Threshold Detection Core
2.5. ADC Logic Simulation Output x
2.5.1. Fixed ADC Logic Simulation Output 2.5.2. User-Specified ADC Logic Simulation Output
3. Intel® MAX® 10 ADC Design Considerations x
3.1. Guidelines: ADC Ground Plane Connection 3.2. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 3.3. Guidelines: Board Design for Analog Input 3.4. Guidelines: Board Design for ADC Reference Voltage Pin
4. Intel® MAX® 10 ADC Implementation Guides x
4.1. Creating Intel® MAX® 10 ADC Design 4.2. Customizing and Generating Modular ADC Core IP Core 4.3. Parameters Settings for Generating ALTPLL IP Core 4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core 4.5. Completing ADC Design
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References x
5.1. Modular ADC Core Parameters Settings 5.2. Modular Dual ADC Core Parameters Settings 5.3. Valid ADC Sample Rate and Input Clock Combination 5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals 5.5. Modular ADC Core Register Definitions 5.6. ADC HAL Device Driver for Nios® Processor
5.1. Modular ADC Core Parameters Settings x
5.1.1. Modular ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.2. Modular Dual ADC Core Parameters Settings x
5.2.1. Modular Dual ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals x
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core 5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core 5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core 5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core 5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core 5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core 5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.5. Modular ADC Core Register Definitions x
5.5.1. Sequencer Core Registers 5.5.2. Sample Storage Core Registers
5.6. ADC HAL Device Driver for Nios® Processor x
5.6.1. Driver API
1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide

7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide

Document Version Intel® Quartus® Prime Version Changes
2024.01.03 22.1
  • Changed the topic: ADC HAL Device Driver for Nios II Gen 2 to ADC HAL Device Driver for Nios Processor.
  • Added new topic: Driver API.
2022.10.31 22.1 Updated ADC HAL Device Driver for Nios II Gen 2 section.
2021.05.04 20.1 Updated the description of the irq signal to specify that it is an output signal that is active high.
2021.01.12 20.1 Updated the table listing the Modular Dual ADC Core IP core channel to pin mapping.
2020.03.17 19.1 Updated the ADC control core timing diagram and removed the accompanying tables.
2019.01.14 18.1
  • Updated the description of the reset_n signal.
  • Updated the IP core names:
    • "Altera Modular ADC" to "Modular ADC Core Intel® FPGA IP"
    • "Altera Modular Dual ADC" to "Modular Dual ADC Core Intel® FPGA IP"
Date Version Changes
December 2017 2017.12.15
  • Added single power supply U324 package.
  • Added a topic that shows the equations and calculation example to convert between analog voltage values and digital representation.
  • Updated the topic about ADC timing to add time calculation examples for the ADC control core based on the sampling rate.
  • Added a note to specify that the Modular ADC Core and Modular Dual ADC Core IP cores support generating only Verilog* simulation scripts. VHDL simulation is not supported.
  • Added note to the topic about the peripheral clock interface signal to specify that the peripheral clock frequency must be at least 25 MHz.
  • Updated the slot numbers of the ADC sample register address offset to correspond to the sequence slot numbers in Intel® Quartus® Prime.
July 2017 2017.07.06 Updated the description of the EOP bit "0" of the Interrupt Status Register (ISR) to improve clarity.
February 2017 2017.02.21 Rebranded as Intel.
January 2017 2017.01.25 Added a topic that lists the actual TSD sampling rate based on the ADC sampling rate selected in the IP core.
October 2016 2016.10.31
  • Updated the topic about the ADC voltage reference to specify that you must use clean external voltage reference with a maximum resistance of 100 Ω.
  • Updated the topic about the ADC sequencer to clarify that "conversion mode" refers to the sequencer conversion mode, namely the single-cycle and continuous ADC conversion modes.
  • Added a related information link to a topic in the Intel® MAX® 10 Clocking and PLL User Guide that lists the availability of PLL1 and PLL3 in different Intel® MAX® 10 devices and packages.
  • Updated various topics throughout the user guide to improve the clarity of descriptions related to the user-specified ADC logic simulation output feature.
  • Updated the VCCVREF pin name to ADC_VREF.
  • Edited the board design guidelines for analog input:
    • Updated text to improve clarity.
    • Updated the Fcutoff @ -3dB recommendation from "five times" to "at least two times" the input frequency.
    • Updated the figure showing the first order active low pass filter example.
May 2016 2016.05.02
  • Removed all preliminary marks.
  • Added new function to specify predefined ADC sampling rate up to 1 MSPS. Previously, the ADC always operate at the maximum sampling rate.
  • Removed link to a workaround to reduce the sampling rate. Now you can set the sampling rate in the IP core parameter editor.
  • Added the ADC Toolkit that supports the Modular ADC Core and Modular Dual ADC Core IP cores.
  • Added feature to simulate ADC output using your own expected output files for each ADC channel except the TSD channel.
  • Corrected the description for bits 11:0 and bits 27:16 of the ADC sample register for Modular ADC Core and Modular Dual ADC Core IP cores. Bits 11:0 and bits 27:16 hold the actual 12 bit sampled data for the storage slot instead of the slot number.
  • Corrected the default value for bit 0 of the interrupt enable register (IER) and interrupt status register (ISR). The default value for M_EOP is 1 and for EOP is 0.
November 2015 2015.11.02
  • Added related information link to Introduction to Altera IP Cores.
  • Added links to instructional videos that demonstrate how to create ADC designs in Intel® MAX® 10 devices.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.11 Updated the board design guidelines for analog input.
May 2015 2015.05.04
  • Added the Modular Dual ADC Core IP core.
  • Removed F672 from the 10M25 device and added ADC information for the E144 package of the 10M04 device:
    • Updated the ADC block counts.
    • Updated the ADC vertical migration support.
    • Updated the ADC channel counts.
  • Updated the table that lists the ADC channel count to list only 8 dual function pins (instead of 16) for the M153 and U169 packages.
  • Updated the ADC vertical migration diagram to clarify that there are single ADC devices with eight and 16 dual function pins.
  • Updated the topic about ADC conversion to specify that in prescaler mode, the analog input in dual and single supply devices can measure up to 3.0 V and 3.6 V, respectively.
  • Updated the ADC IP core architecture figures to include features for the dual ADC IP core.
  • Added information and topics about the response merge and dual ADC synchronizer micro cores.
  • Removed notes about contacting Altera for the ADC pin RLC filter design.
  • Updated the ADC prescaler topic to change the ADC2 channel that supports prescaler from channel 16 to channel 17.
  • Updated the diagram that shows the ADC timing:
    • To clarify that the numbers are hexadecimal numbers.
    • Relabeled the signals to match the command and response interface signal names.
  • Updated the RC constant and filter value and the filter design example figure to clarify the source of the example values.
  • Added guidelines for setting up the sequencer in dual ADC mode.
  • Added topics that list the mapping of Modular ADC Core and Modular Dual ADC Core IP cores channel names to Intel® MAX® 10 device pin names.
  • Corrected the address offset of the interrupt enable register (from 0x41 to 0x40) and interrupt status register (from 0x40 to 0x41) for the sample storage core.
  • Updated the sample storage core registers table to include registers for Modular Dual ADC Core.
  • Removed statements about availability of the threshold trigger feature in a future version of the Intel® Quartus® Prime software. The feature is now available from version 15.0 of the software.
December 2014 2014.12.15
  • Added ADC prescaler block diagram.
  • Replaced the ADC continuous conversion timing diagram with the ADC timing diagram.
  • Corrected a minor error in the example in the topic about the sample storage core.
  • Added information that the ADC TSD measures the temperature using a 64-samples running average method.
  • Updated majority of the temperature codes in the table that lists the temperature code conversion.
  • Added chapter that provides the ADC design considerations.
  • Removed mention of value "0" for values allowed for the number of sequencer slots used in Modular ADC Core IP core parameter editor. Only values 1 to 64 are allowed.
  • Removed the statement about enabling and disabling additional ADC response interface or debugging in the topic about the Modular ADC Core IP core configuration variants. You can enable or disable the debug path in the parameter editor.
  • Removed the debug paths diagrams for each ADC core configuration.
  • Removed the statement about using the sequencer core to trigger recalibration. The ADC is automatically recalibrated when it switches from normal sensing mode to temperature sensing mode.
  • Edited text to clarify about routing power or ground traces if power or ground plane is not possible.
  • Updated the total RC constant values in the table that shows the RC constant and filter values calculation.
  • Corrected spelling for "prescaler".
September 2014 2014.09.22 Initial release.
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