Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 1/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Analog to Digital Converter Overview 2. Intel® MAX® 10 ADC Architecture and Features 3. Intel® MAX® 10 ADC Design Considerations 4. Intel® MAX® 10 ADC Implementation Guides 5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References 6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
1. Intel® MAX® 10 Analog to Digital Converter Overview x
1.1. ADC Block Counts in Intel® MAX® 10 Devices 1.2. ADC Channel Counts in Intel® MAX® 10 Devices 1.3. Intel® MAX® 10 ADC Vertical Migration Support 1.4. Intel® MAX® 10 Single or Dual Supply Devices 1.5. Intel® MAX® 10 ADC Conversion
1.5. Intel® MAX® 10 ADC Conversion x
1.5.1. Voltage Representation Conversion
2. Intel® MAX® 10 ADC Architecture and Features x
2.1. Intel® MAX® 10 ADC Hard IP Block 2.2. Modular ADC Core and Modular Dual ADC Core IP Cores 2.3. Intel FPGA ADC HAL Driver 2.4. ADC Toolkit for Testing ADC Performance 2.5. ADC Logic Simulation Output
2.1. Intel® MAX® 10 ADC Hard IP Block x
2.1.1. ADC Block Locations 2.1.2. Single or Dual ADC Devices 2.1.3. ADC Analog Input Pins 2.1.4. ADC Prescaler 2.1.5. ADC Clock Sources 2.1.6. ADC Voltage Reference 2.1.7. ADC Temperature Sensing Diode 2.1.8. ADC Sequencer 2.1.9. ADC Timing
2.1.7. ADC Temperature Sensing Diode x
2.1.7.1. Temperature Measurement Code Conversion 2.1.7.2. Temperature Measurement Sampling Rate
2.1.8. ADC Sequencer x
2.1.8.1. Guidelines: ADC Sequencer in Modular Dual ADC Core IP Core
2.2. Modular ADC Core and Modular Dual ADC Core IP Cores x
2.2.1. Modular ADC Core IP Core Configuration Variants 2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
2.2.1. Modular ADC Core IP Core Configuration Variants x
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage 2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection 2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage 2.2.1.4. Configuration 4: ADC Control Core Only
2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture x
2.2.2.1. ADC Control Core 2.2.2.2. Sequencer Core 2.2.2.3. Sample Storage Core 2.2.2.4. Response Merge Core 2.2.2.5. Dual ADC Synchronizer Core 2.2.2.6. Threshold Detection Core
2.5. ADC Logic Simulation Output x
2.5.1. Fixed ADC Logic Simulation Output 2.5.2. User-Specified ADC Logic Simulation Output
3. Intel® MAX® 10 ADC Design Considerations x
3.1. Guidelines: ADC Ground Plane Connection 3.2. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 3.3. Guidelines: Board Design for Analog Input 3.4. Guidelines: Board Design for ADC Reference Voltage Pin
4. Intel® MAX® 10 ADC Implementation Guides x
4.1. Creating Intel® MAX® 10 ADC Design 4.2. Customizing and Generating Modular ADC Core IP Core 4.3. Parameters Settings for Generating ALTPLL IP Core 4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core 4.5. Completing ADC Design
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References x
5.1. Modular ADC Core Parameters Settings 5.2. Modular Dual ADC Core Parameters Settings 5.3. Valid ADC Sample Rate and Input Clock Combination 5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals 5.5. Modular ADC Core Register Definitions 5.6. ADC HAL Device Driver for Nios® Processor
5.1. Modular ADC Core Parameters Settings x
5.1.1. Modular ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.2. Modular Dual ADC Core Parameters Settings x
5.2.1. Modular Dual ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals x
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core 5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core 5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core 5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core 5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core 5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core 5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.5. Modular ADC Core Register Definitions x
5.5.1. Sequencer Core Registers 5.5.2. Sample Storage Core Registers
5.6. ADC HAL Device Driver for Nios® Processor x
5.6.1. Driver API
1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide

5.2. Modular Dual ADC Core Parameters Settings

There are three groups of options: General, Channels, and Sequencer.
Table 21.   Modular Dual ADC Core Parameters - General
Parameter Allowed Values Description
Core Variant
  • Standard sequencer with Avalon-MM sample storage
  • Standard sequencer with Avalon-MM sample storage and threshold violation detection
  • Standard sequencer with external sample storage
  • ADC control core only

Selects the core configuration for the Modular Dual ADC Core IP core.

ADC Sample Rate 25 kHz, 50 kHz, 100 kHz, 200 kHz, 250 kHz, 500 kHz, and 1 MHz

Specifies the ADC sampling rate. The sampling rate you select affects which ADC input clock frequencies are available.

Refer to the related information for more details about the sampling rate and the required settling time.

ADC Input Clock 2 MHz, 10 MHz, 20 MHz, 40 MHz, and 80 MHz

Specifies the frequency of the PLL clock counter zero (c0) clock supply for the ADC core clock.

  • You must configure the c0 of the first ALTPLL IP core that you instantiate to output one of the frequencies in the allowed values list.
  • Connect the ALTPLL c0 output signal to the Modular Dual ADC Core clk_in_pll_c0 input signal.

For valid ADC sampling rate and input clock frequencies combinations, refer to the related information.

Reference Voltage (ADC1 or ADC2)
  • External
  • Internal

Specifies the source of voltage reference for the ADC:

  • External—uses ADC_VREF pin as the voltage reference source.
  • Internal—uses the on-chip 2.5 V (3.0/3.3V on voltage-regulated devices) as the voltage reference source.
External Reference Voltage
  • Dual supply devices: up to 2.5 V
  • Single supply devices: up to 3.63 V

Specifies the voltage of ADC_VREF pin if you use it as reference voltage to the ADC.

Enable user created expected output file
  • Enabled
  • Disabled
 Specifies the source of output data for ADC logic simulation:
  • Enabled—uses the stimulus input file you provide for each ADC channel, except the TSD channel, to simulate the output data.
  • Disabled—uses fixed expected output data for all ADC channels. This is the default setting.

For more information about user-specified ADC logic simulation output, refer to the related information.

Table 22.   Modular Dual ADC Core Parameters - Channels This group of parameters is divided into two main tabs for ADC1 and ADC2. For each tab, there are several channel tabs—one for each channel, and one tab for the TSD in ADC1.
Parameter Allowed Values Description

Use Channel 0 or 9 (Dedicated analog input pin - ANAIN)

(CH0 tab for ADC1 or CH9 tab for ADC2)
  • On
  • Off

Enables the dedicated analog input pin for ADC1 or ADC2.

User created expected output file — Specifies user-created stimulus input file to simulate the output data for the channel.

This option is available for each enabled channel except the TSD if you select Enable user created expected output file.

Use Channel N

(Each channel in its own tab)
  • On
  • Off

Enables the dual-function analog input, where N is:

  • Channels 1 to 8 for ADC1
  • Channels 10 to 17 for ADC2

Use on-chip TSD

(TSD tab in ADC1 only)
  • On
  • Off

Specifies that the IP core reads the built-in temperature sensor in ADC1.

If you turn on this option, the ADC sampling rate is up to 50 kHz when it reads the temperature measurement. After it completes the temperature reading, the ADC sampling rate is up to 1 MHz.

Note: If you select the TSD for a sequencer slot in ADC1, select NULL for the same sequencer slot number in ADC2.

Enable Maximum threshold for Channel N

(Each channel in its own tab)
  • On
  • Off

Enables the maximum threshold feature for the channel.

This option is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enable Maximum threshold for on-chip TSD

(TSD tab)
  • On
  • Off

Enables the maximum threshold feature for the TSD.

This option is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enter Maximum Threshold for Channel N

(Each channel in its own tab, including channel 0)

Depends on reference voltage

Specifies the maximum threshold value in Volts.

This setting is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enter Maximum Threshold for on-chip TSD

(TSD tab)

 —

Specifies the maximum threshold value in Celsius.

This setting is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enable Minimum threshold for Channel N

(Each channel in its own tab, including channel 0)

  • On
  • Off

Enables the minimum threshold feature for the channel.

This option is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enable Minimum threshold for on-chip TSD

(TSD tab)
  • On
  • Off

Enables the minimum threshold feature for the TSD.

This option is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enter Minimum Threshold for Channel N

(Each channel in its own tab, including channel 0)

Depends on reference voltage

Specifies the minimum threshold value in Volts.

This setting is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enter Minimum Threshold for on-chip TSD

(TSD tab)

 —

Specifies the minimum threshold value in Celsius.

This setting is available only if you select the Standard sequencer with Avalon-MM sample storage and threshold violation detection core variant.

Enable Prescaler for Channel N
  • On
  • Off

Enables the prescaler function, where N is:

  • Channel 8 in ADC1
  • Channel 17 in ADC2
Table 23.   Modular Dual ADC Core Parameters - Sequencer
Parameter Allowed Values Description
Number of slot used 1 to 64

Specifies the number of conversion sequence slots to use for both ADC1 and ADC2.

The Conversion Sequence Channels section displays the slots available for ADC1 and ADC2 according to the number of slots you select here.

Slot N Enabled channel number (CH N)

Specifies which enabled ADC channel to use for the slot in the sequence.

The selection option lists the ADC channels that you turned on in the Channels parameter group for ADC1 and ADC2.

Note: If you select the TSD for a sequencer slot in ADC1, select NULL for the same sequencer slot number in ADC2.

Section Content
Modular Dual ADC Core IP Core Channel Name to Intel MAX 10 Device Pin Name Mapping

Related Information
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