CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.19.6. Interface to the External Reset Controller

Table 48.   CPRI Intel® FPGA IP Core External Reset Controller Interface SignalsThe CPRI IP core requires that you generate and connect at least one external transceiver reset controller. These signals are not available in Intel® Stratix® 10 E-tile and Intel Agilex® 7 E- tile device variations since the PHY includes the transceiver reset controller.

Signal Name

Direction

Description

xcvr_tx_analogreset

Input

Analog reset to transmitter from external reset controller.

xcvr_tx_digitalreset

Input

Digital reset to transmitter from external reset controller.

xcvr_tx_cal_busy

Output

Indicates to external reset controller that the transmitter is still busy with the calibration process.

xcvr_rx_analogreset

Input

Analog reset to receiver from external reset controller.

xcvr_rx_digitalreset

Input

Digital reset to receiver from external reset controller.

xcvr_rx_cal_busy

Output

Indicates to external reset controller that the receiver is still busy with the calibration process.

xcvr_reset_tx_ready

Input

Indicates the Tx reset controller reset sequence is completed. When this signal is asserted, the IP core begins a reset of the IP core Tx path.
xcvr_reset_rx_ready

Input

Indicates the Rx reset controller reset sequence is completed. When this signal is asserted, the IP core begins a reset of the IP core Rx path.
xcvr_rx_analogreset_stat

Output

This signal is only available in Intel® Stratix® 10 L-and H-tile device variations.
xcvr_rx_digitalreset_stat

Output

This signal is only available in Intel® Stratix® 10 L-and H-tile device variations. This signal needs to be connected to reset controllers.
xcvr_tx_analogreset_stat

Output

This signal is only available in Intel® Stratix® 10 L-and H-tile device variations. This signal needs to be connected to reset controllers.
xcvr_tx_digitalreset_stat

Output

This signal is only available in Intel® Stratix® 10 L-and H-tile device variations. This signal needs to be connected to reset controllers.