CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Public

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3.5.3. Auxiliary Latency Cycles

Intel® provides configurable write latency on the AUX TX interface and other direct TX interfaces to support user logic with sufficient advance notice of the position in the CPRI frame. The processing time that user logic requires after determining the current position in the CPRI frame is implementation specific, and the default write latency of a single cpri_clkout cycle might not be adequate. Using the Auxiliary and direct interfaces write latency cycle(s) parameter, you can set the write latency to the number of clock cycles required for your system to process data before sending it on the AUX TX interface or other direct TX interface.

In the CPRI parameter editor, you can specify a non-zero number of Auxiliary and direct interfaces write latency cycle(s) to increase the write latency on the AUX TX interface and other direct TX interfaces to the CPRI IP.

The write latency is the number of cpri_clkout cycles from when the aux_tx_seq output signal has the value of n to when user logic must write data to the AUX TX interface to target the corresponding position in the CPRI frame. For other direct interfaces, the IP core notifies user logic when it is ready for input and the user does not need to monitor the aux_tx_seq signal. However, the Auxiliary latency cycle(s) value does apply to all of the direct interfaces.

When Auxiliary and direct interfaces write latency cycle(s) has the default value of zero, the write latency on the direct TX interfaces is one cpri_clkout cycle. When Auxiliary and direct interfaces write latency cycle(s) has the value of N, the write latency is (1+N) cpri_clkout cycles.

User logic is responsible to ensure that the data presented to the Intel® FPGA IP core on the AUX TX interface is presented at the correct write latency relative to the AUX TX interface synchronization signals.

Note: You cannot simply write to the AUX TX interface with a consistent write latency that you determine after configuring your Intel® FPGA IP core. If you do not specify the correct write latency in the CPRI parameter editor, the data you present on the AUX TX interface cannot fill the correct position in the target CPRI frame. To ensure the write latency offset is implemented correctly in the Intel® FPGA IP core, you must set the parameter.
Figure 34. AUX Interface Transmit Write LatencyIllustrates the transmit write latency on the AUX interface when Auxiliary and direct interfaces write latency cycle(s) has the value of 0. If you specify a non-zero value for this parameter, the latency increases from the default latency of one cpri_clkout cycle to 1 plus the number of cycles you specify.

In this example, the CPRI line bit rate is 6.144 Gbps, so that the control word is 10 bytes. User logic masks the control word, so that the Intel® FPGA IP core does not receive the control words from the AUX interface.