CPRI Intel® FPGA IP User Guide

Download PDF
ID 683595
Date 5/19/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. System PLL Connections for the Intel Agilex® 7 F-tile Variations 2.5.3. Adding the Reset Controller 2.5.4. Adding the Transceiver Reconfiguration Controller 2.5.5. Adding the Off-Chip Clean-Up PLL 2.5.6. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.7. Transceiver PLL Calibration 2.5.8. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces

The CPRI IP can communicate with the surrounding design through multiple optional interfaces that provide direct access to all or part of the CPRI frame.

Table 53.  L1 Direct Access Interface SignalsThe Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.

Signal Name

Direction

Description

auxN_rx_ctrl[C:0] Output AUX RX interface status signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_rx_rfp Output
auxN_rx_hfp Output
auxN_rx_bfn[11:0] Output
auxN_rx_z[7:0] Output
auxN_rx_x[7:0] Output
auxN_rx_seq[6:0] Output
auxN_rx_data[D:0] Output AUX RX interface data signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_rx_ctrl[C:0] Output
auxN_tx_sync_rfp Input AUX TX interface control and status signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_tx_error Output
auxN_tx_ctrl[C:0] Output
auxN_tx_err[C:0] Output
auxN_tx_rfp Output
auxN_tx_hfp Output
auxN_tx_bfn[11:0] Output
auxN_tx_z[7:0] Output
auxN_tx_x[7:0] Output
auxN_tx_seq[6:0] Output
auxN_tx_data[D:0] Input AUX TX interface data signals

These signals are available only if you turn on Enable auxiliary interface in the CPRI parameter editor.

auxN_tx_mask[D:0] Input
auxN_tx_ctrl[C:0] Output
iqN_rx_valid[C:0] Output Direct IQ RX interface

These signals are available only if you turn on Enable direct IQ mapping interface in the CPRI parameter editor.

iqN_rx_data[D:0] Output
iqN_tx_ready[C:0] Output Direct IQ TX interface

These signals are available only if you turn on Enable direct IQ mapping interface in the CPRI parameter editor.

iqN_tx_valid[C:0] Input
iqN_tx_data[D:0] Input
ctrlN_axc_rx_valid[C:0] Output Direct Ctrl_AxC RX interface

These signals are available only if you turn on Enable direct ctrl_axc access interface in the CPRI parameter editor.

ctrlN_axc_rx_data[D:0] Output
ctrlN_axc_tx_ready[C:0] Output Direct Ctrl_AxC TX interface

These signals are available only if you turn on Enable direct ctrl_axc access interface in the CPRI parameter editor.

ctrl_axc_tx_valid[3:0] Input
ctrlN_axc_tx_data[D:0] Input
vsN_rx_valid[C:0] Output Direct VS RX interface

These signals are available only if you turn on Enable direct vendor specific access interface in the CPRI parameter editor.

vsN_rx_data[D:0] Output
vsN_tx_ready[C:0] Output Direct VS TX interface

These signals are available only if you turn on Enable direct vendor specific access interface in the CPRI parameter editor.

vsN_tx_valid[C:0] Input
vsN_tx_data[D:0] Input
rtvsN_rx_valid Output Direct RTVS RX interface

These signals are available only if you turn on Enable direct real-time vendor specific interface in the CPRI parameter editor.

rtvsN_rx_data[D:0] Output
rtvsN_tx_ready Output Direct RTVS TX interface

These signals are available only if you turn on Enable direct real-time vendor specific interface in the CPRI parameter editor.

rtvsN_tx_valid Input
rtvsN_tx_data[D:0] Input
hdlc_rx_valid Output Direct HDLC serial RX interface

These signals are available only if you turn on Enable HDLC serial interface in the CPRI parameter editor.

hdlc_rx_data Output
hdlc_tx_ready Output Direct HDLC serial TX interface

These signals are available only if you turn on Enable HDLC serial interface in the CPRI parameter editor.

hdlc_tx_valid Input
hdlc_tx_data Input
z130_local_lof Output Direct L1 control and status interface

These signals are available only if you turn on Enable direct Z.130.0 alarm bits access interface in the CPRI parameter editor.

z130_local_los Output
z130_sdi_assert Input
z130_local_rai Output
z130_reset_assert Input
z130_remote_lof Output
z130_remote_los Output
z130_sdi_req Output
z130_remote_rai Output
z130_reset_req Output
Related Information
Level Two Title