CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.17.3. Extended Delay Measurement Interface

Table 41.  Extended Delay Measurement Interface Signals

Signal Name

Direction

Description

ex_delay_clk Input Clock for extended delay measurement.
ex_delay_reset_n Input Resets the extended delay measurement block. This signal is active low.

This reset signal is associated with the ex_delay_clk clock.

latency_sclk Input Clock for extended delay measurement of Intel® Stratix® 10 hard FIFOs.

You can (but need not) drive this clock at the same frequency as ex_delay_clk.

latency_sreset_n Input Resets the extended delay measurement soft logic for the Intel® Stratix® 10 hard FIFOs. This signal is active low.

This reset signal is associated with the latency_sclk clock.