CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
5. CPRI Intel® FPGA IP Core Registers x
5.1. INTR Register 5.2. L1_STATUS Register 5.3. L1_CONFIG Register 5.4. BIT_RATE_CONFIG Register 5.5. PROT_VER Register 5.6. TX_SCR Register 5.7. RX_SCR Register 5.8. CM_CONFIG Register 5.9. CM_STATUS Register 5.10. START_UP_SEQ Register 5.11. START_UP_TIMER Register 5.12. FLSAR Register 5.13. CTRL_INDEX Register 5.14. TX_CTRL Register 5.15. RX_CTRL Register 5.16. RX_ERR Register 5.17. RX_BFN Register 5.18. LOOPBACK Register 5.19. TX_DELAY Register 5.20. RX_DELAY Register 5.21. TX_EX_DELAY Register 5.22. RX_EX_DELAY Register 5.23. ROUND_TRIP_DELAY Register 5.24. XCVR_BITSLIP Register 5.25. DELAY_CAL_STD_CTRL1 Register 5.26. DELAY_CAL_STD_CTRL2 Register 5.27. DELAY_CAL_STD_CTRL3 Register 5.28. DELAY_CAL_STD_CTRL4 Register 5.29. DELAY_CAL_STD_CTRL5 Register 5.30. DELAY_CAL_STD_STATUS Register 5.31. DELAY_CAL_RTD Register 5.32. XCVR_TX_FIFO_DELAY Register 5.33. XCVR_RX_FIFO_DELAY Register 5.34. IP_INFO Register 5.35. DEBUG_STATUS Register
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

2.8. Running the Design Example

To run the synthesizable hardware design example on the supported devices, you must supply the appropriate clock top level (tb_top) input ports with fixed frequencies as specified below:

  • clk_100: 100MHz
  • sampling_refclk: 100MHz (Only for the Intel® Agilex™ F-Tile devices)
  • cdr_refclk: Supply clock with frequency for initial bit rate chosen according to the folllowing table, except for E-Tile device. Supply 153.60MHz clock for E-Tile device.
  • cdr_refclk1: Supply secondary clock with frequency for target bit rate according to the folllowing table (Only for the Intel® Stratix® 10 H-Tile or Intel® Arria® 10 devices when the Rate Negotiation feature is enabled).
    • If selected target bit rate for rate negotiation uses the same reference clock frequency as initial bit rate, supply cdr_refclk and cdr_refclk1 with the same clock frequency.
    • If one or more selected target bit rate for rate negotiation uses different reference clock frequency as initial bit rate, supply cdr_refclk with the frequency required for initial bit rate and supply cdr_refclk1 with the different secondary frequency.
  • ehip_ref_clk: Supply clock with frequency for initial bit rate chosen aaccording to the folllowing table (Only for F-Tile and E-Tile devices).
  • ehip_ref_clk1: Supply secondary clock with frequency for target bit rate according to the folllowing table (Only for F-Tile and E-Tile devices when Rate Negotiation feature is enabled).
    • If selected target bit rate for rate negotiation uses the same reference clock frequency as initial bit rate, supply ehip_ref_clk and ehip_ref_clk1 with the same clock frequency.
    • If one or more selected target bit rate for rate negotiation uses different reference clock frequency as initial bit rate, supply ehip_ref_clk with the frequency required for initial bit rate and supply ehip_ref_clk1 with the different secondary frequency.
  • aib_pll_refclk: 156.25MHz (Only for F-Tile and E-Tile devices).
Table 18.  Reference Clock Frequency Requirement
Initial or Target Bit rate (Mbits/s) F-Tile and E-Tile Device (MHz) Other Device (MHz)
24330.24 184.32 253.44
12165.12 184.32 253.44
10137.60 184.32 253.44
9830.40 153.60 245.76
8110.08 184.32 253.44
6144.00 153.60 245.76
4915.20 153.60 245.76
3072.00 153.60 245.76
2457.60 153.60 245.76
1228.80 153.60 245.76
614.40 153.60 245.76

To run the CPRI Intel® FPGA IP demonstration testbench, follow these steps.

  1. In the Quartus® Prime software IP Catalog, select the CPRI Intel® FPGA IP and click Add.
  2. When prompted, you can specify any output file type (HDL). This setting is relevant only for synthesis and does not impact simulation of the demonstration testbench.
  3. In the CPRI parameter editor, set the following parameter values:
    Table 19.   CPRI Intel® FPGA IP Core Variation for Demonstration TestbenchThe testbench scripts require that you set these values in the CPRI parameter editor before you click Generate Example Design. The scripts generate the DUT but they require that you provide the parameter values.
    Parameter Value
    Line bit rate (Mbit/s) Any value the device family supports.
    Synchronization mode Master
    Operation mode Any available mode
    Transmitter local clock division factor 1
    Number of receiver CDR reference clock(s) 1
    Receiver CDR reference clock frequency (MHz)

    253.44 if the Line bit rate is 8.11008 or 10.1376 or 12.16512 Gbps and the IP targets the Intel® Stratix® 10 device family

    368.64 if the Line bit rate is 24.33024 Gbps and the IP targets the Intel® Stratix® 10 device family

    253.44 if the Line bit rate is 8.11008 or 10.1376 Gbps and the IP targets the Intel® Arria® 10 device family

    253.44 if the Line bit rate is 8.11008 or 10.1376 Gbps and the IP targets a 28-nm device family

    253.44 if the Line bit rate is 8.11008 Gbps and the IP targets Arria® V GZ device family

    307.2 for all other cases
    Core clock source input Internal or External
    Recovered clock source PMA if the Line bit rate is 10.1376 Gbps and IP core targets the Stratix V device family; PCS otherwise
    Receiver soft buffer depth (value shown is log2 of actual depth) 6
    Enable line bit rate auto-negotiation Turn on or off
    Enable line bit rate auto-negotiation down to 614.4 Mbps Not available
    Management (CSR) interface standard Avalon® -MM
    Avalon-MM interface addressing type Word
    Auxiliary and direct interfaces write latency cycle(s) 0
    Enable auxiliary interface Turn on or Turn off
    Enable resyncronization of CPRI radio frame number to desired value Turn on or Turn off
    Enable all control word access via management interface Turn off
    Enable direct Z.130.0 alarm bits access interface Turn off
    Enable direct ctrl_axc access interface Turn on or Turn off
    Enable direct vendor specific access interface Turn on or Turn off
    Enable direct real-time vendor specific interface Turn on or Turn off
    Enable start-up sequence state machine Turn off
    Enable protocol version and C&M channel setting auto-negotiation Not available
    Enable direct IQ mapping interface Turn on or Turn off
    Enable HDLC serial interface Turn on or Turn off
    Ethernet PCS interface NONE, MII or GMII
    L2 Ethernet PCS Tx/Rx FIFO depth (value shown is log2 of actual depth) 8
    Enable L1 debug interfaces Turn off
    Enable Native PHY Debug Master Endpoint (NPDME), transceiver capability, control and status registers access Turn off
    Enable transceiver PMA serial forward loopback path Turn off
    Enable parallel forward loopback paths Turn off
    Enable parallel reversed loopback paths Turn off
    Enable single-trip delay calibration Not available
    Enable round-trip delay calibration Turn off
    Round-trip delay calibration FIFO depth Not available
    Language for top-level simulation file
    • Verilog
    • VHDL
  4. In the CPRI parameter editor, click the Generate Example Design button and specify the desired location of the testbench.
  5. Change directory to <your_ip>/setup_scripts/<simulator_vendor> .
  6. For Intel Agilex F-tile devices, perform these additional steps:
    1. Navigate to the <your_ip>/ip_components directory and perform these two commands:
      quartus_ipgenerate --run_default_mode_op tb_top -c tb_top
      quartus_tlg tb_top
      Alternately, you may open the tb_top.qpf project in Intel® Quartus® Prime and perform the compilation until support logic generation stage.
    2. Navigate to the <your_ip>/simulation/setup_scripts directory.
    3. Perform the following command:
      ip-setup-simulation --use-relative-paths --quartus-project=../ip_components/tb_top.qpf
  7. If you are using a simulator that requires that you open a user interface, open your target simulator.
    Note: You must select a simulator that is supported by the Intel® Quartus® Prime software version you are using.
  8. Execute the simulation script available for your simulation in the directory.
    • In the Mentor Graphics ModelSim simulator, type do msim_commands.do
  9. You can modify testbench parameters from a file params_list.sv, located at <your_ip>/testbench location.
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