CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
5. CPRI Intel® FPGA IP Core Registers x
5.1. INTR Register 5.2. L1_STATUS Register 5.3. L1_CONFIG Register 5.4. BIT_RATE_CONFIG Register 5.5. PROT_VER Register 5.6. TX_SCR Register 5.7. RX_SCR Register 5.8. CM_CONFIG Register 5.9. CM_STATUS Register 5.10. START_UP_SEQ Register 5.11. START_UP_TIMER Register 5.12. FLSAR Register 5.13. CTRL_INDEX Register 5.14. TX_CTRL Register 5.15. RX_CTRL Register 5.16. RX_ERR Register 5.17. RX_BFN Register 5.18. LOOPBACK Register 5.19. TX_DELAY Register 5.20. RX_DELAY Register 5.21. TX_EX_DELAY Register 5.22. RX_EX_DELAY Register 5.23. ROUND_TRIP_DELAY Register 5.24. XCVR_BITSLIP Register 5.25. DELAY_CAL_STD_CTRL1 Register 5.26. DELAY_CAL_STD_CTRL2 Register 5.27. DELAY_CAL_STD_CTRL3 Register 5.28. DELAY_CAL_STD_CTRL4 Register 5.29. DELAY_CAL_STD_CTRL5 Register 5.30. DELAY_CAL_STD_STATUS Register 5.31. DELAY_CAL_RTD Register 5.32. XCVR_TX_FIFO_DELAY Register 5.33. XCVR_RX_FIFO_DELAY Register 5.34. IP_INFO Register 5.35. DEBUG_STATUS Register
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

3.5.1. AUX Interface Signals

Table 24.  AUX Interface SignalsIf you turn on Enable auxiliary interface in the CPRI parameter editor, the AUX interface is available. This interface allows access to the entire CPRI frame and has the highest priority among the L1 interfaces.

You can alter the transmit write latency with the Auxiliary and direct interfaces write latency cycle(s) parameter. The default transmit latency, when Auxiliary and direct interfaces write latency cycle(s) has the value of zero, is one cpri_clkout cycle. You can specify additional latency cycles.

The Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.

All interface signals are clocked by the cpri_clkout clock.

AUX RX Interface Status Signals

Signal Name

Direction

Description

auxN_rx_rfp Output Synchronization pulse for start of 10 ms radio frame. The pulse occurs at the start of the radio frame on the AUX RX interface.
auxN_rx_hfp Output Synchronization pulse for start of hyperframe. The pulse occurs at the start of the hyperframe on the AUX RX interface.
auxN_rx_bfn[11:0] Output Current radio frame number on the AUX RX interface.
auxN_rx_z[7:0] Output Current hyperframe number on the AUX RX interface. Value is in the range 0–149.
auxN_rx_x[7:0] Output Index number of the current basic frame in the current hyperframe on the AUX RX interface. Value is in the range 0–255.
auxN_rx_seq[6:0] Output Index number of the current 32-bit word in the current basic frame on the AUX RX interface. The value range depends on the current CPRI line bit rate:
  • 0.6144 Gbps: range is 0–3
  • 1.2288 Gbps: range is 0–7
  • 2.4576 Gbps: range is 0–15
  • 3.0720 Gbps: range is 0–19
  • 4.9152 Gbps: range is 0–31
  • 6.1440 Gbps: range is 0–39
  • 8.11008 Gbps: range is 0–63
  • 9.8304 Gbps: range is 0–63
  • 10.1376 Gbps: range is 0–79
For 64-bit word, the index number value range is generally half of the value range for 32-bit word:
  • 8.11008 Gbps: range is 0–31
  • 10.1376 Gbps: range is 0–39
  • 12.16512 Gbps: range is 0–47
  • 24.33024 Gbps: range is 0–95

12.16512 and 24.33024 Gbps CPRI line rates uses 64-bit interface. 8.11008 and 10.1376 Gbps CPRI line rates uses 64-bit interface when aut-rate negotiated from 12.16512/24.33024 Gbps

AUX RX Interface Data Signals

Signal Name

Direction

Description

auxN_rx_data[D:0] Output Data the IP core presents on the AUX link. Data is transmitted in 32-bit words. Byte [31:24] is transmitted first and byte [7:0] is transmitted last.
auxN_rx_ctrl[C:0] Output Control slots indicator. Each asserted bit indicates that the corresponding byte position in aux_rx_data holds a byte from a CPRI control word.
AUX TX Interface Control and Status Signals

Signal Name

Direction

Description

auxN_tx_sync_rfp Input Synchronization input used in REC master to control the start of a new 10 ms radio frame. Asserting this signal resets the frame synchronization machine. The CPRI IP uses the rising edge of the pulse for synchronization. Rising edge of this signal is synchronous to the rising edge of cpri_clkout.
aux_bfn_resync_value [11:0] Input Enables the resynchronization of CPRI radio frame number to a desired value. It is for resynchronization of outgoing CPRI radio frame number with nodeB Frame Number(BFN). This signal takes effect on next clock cycle after positive edge of auxN_tx_sync_rfp.
auxN_tx_err[C:0] Output Indicates that in the previous cpri_clkout cycle, aux_tx_mask bits masked one or more control words in the target CPRI frame. Each bit in aux_tx_err indicates whether the corresponding byte in the 32-bit value on aux_tx_data overwrites a control word in the target CPRI frame.
auxN_tx_rfp Output Synchronization pulse for start of 10 ms radio frame. The pulse occurs at the start of the radio frame on the AUX TX interface.
auxN_tx_hfp Output Synchronization pulse for start of hyperframe. The pulse occurs at the start of the hyperframe on the AUX TX interface.
auxN_tx_bfn[11:0] Output Current radio frame number on the AUX TX interface.
auxN_tx_z[7:0] Output Current hyperframe number on the AUX TX interface. Value is in the range 0–149.
auxN_tx_x[7:0] Output Index number of the current basic frame in the current hyperframe on the AUX TX interface. Value is in the range 0–255. The number transitions to 0 after 1 clock of the aux_tx_sync_rfp rising edge.
auxN_tx_seq[6:0] Output Index number of the current 32-bit word in the current basic frame on the AUX TX interface.

The value range depends on the current CPRI line bit rate:

  • 0.6144 Gbps: range is 0–3
  • 1.2288 Gbps: range is 0–7
  • 2.4576 Gbps: range is 0–15
  • 3.0720 Gbps: range is 0–19
  • 4.9152 Gbps: range is 0–31
  • 6.1440 Gbps: range is 0–39
  • 8.11008 Gbps: range is 0–63
  • 9.8304 Gbps: range is 0–63
  • 10.1376 Gbps: range is 0–79
For 64-bit word, the index number value range is generally half of the value range for 32-bit word:
  • 8.11008 Gbps: range is 0–31
  • 10.1376 Gbps: range is 0–39
  • 12.16512 Gbps: range is 0–47
  • 24.33024 Gbps: range is 0–95

12.16512 and 24.33024 Gbps CPRI line rates uses 64-bit interface. 8.11008 and 10.1376 Gbps CPRI line rates uses 64-bit interface when aut-rate negotiated from 12.16512/24.33024 Gbps

AUX TX Interface Data Signals

Signal Name

Direction

Description

auxN_tx_data[D:0] Input Data the IP core receives on the AUX TX interface. The data is aligned with aux_tx_seq with a write delay of one cpri_clkout cycle plus the number of additional cpri_clkout cycles you specify as the value of the Auxiliary and direct interfaces write latency cycle(s) parameter.

User logic is responsible to ensure that the write data in aux_tx_data is aligned with the write latency value of the Auxiliary and direct interfaces write latency cycle(s) parameter.

Data is received in 32-bit words. For correct transmission in the CPRI frame, you must send byte [31:24] first and byte [7:0] last.

auxN_tx_mask[D:0] Input Bit mask for insertion of data from aux_tx_data in the target CPRI frame.

This signal aligns with aux_tx_data and therefore, aligns with aux_tx_seq with a delay of one cpri_clkout cycle plus the number of additional cpri_clkout cycles you specify as the value of the Auxiliary and direct interfaces write latency cycle(s) parameter.

Assertion of a bit in this mask overrides insertion of data to the corresponding bit in the target CPRI frame from any other source. Therefore, you must deassert the mask bits during K28.5 character or /S/ /T/ insertion in the outgoing CPRI frame, which occurs when Z=X=0. If you do not deassert the mask bits during K28.5 or /S/ /T/ character insertion in the outgoing CPRI frame, the aux_tx_err output signal is asserted in the following cpri_clkout cycle.

auxN_tx_ctrl[C:0] Output Control slots indicator. Each asserted bit indicates that the corresponding byte position, as indicated by aux_tx_seq, should hold a CPRI control word in the target CPRI frame.
Figure 25. AUX RX Interface Timing DiagramAUX RX interface behavior in a CPRI IP core running at 0.6144 Gbps.


Figure 26. CPRI REC Master Response to aux_tx_sync_rfp Resynchronization PulseAsserting aux_tx_sync_rfp resets the hyperframe and basic frame numbers in an REC master CPRI IP. Shown for a CPRI IP core running at 0.6144 Gbps.


Figure 27. CPRI REC Master Response When Enable Resynchronization of CPRI Radio Frame Number to Desired Value
Figure 28. AUX TX Interface Timing Diagram with One Auxiliary Latency CycleExpected behavior on the AUX TX interface of a CPRI IP running at 0.6144 Gbps. Illustrates the effect of setting the Auxiliary and direct interfaces write latency cycle(s) parameter to a a non-zero value. Shown for a CPRI IP with Auxiliary and direct interfaces write latency cycle(s) set to the value of 1.


Figure 29. AUX TX Interface Timing Diagram with Four Auxiliary Latency CyclesExpected behavior on the AUX TX interface of a CPRI IP running at 0.6144 Gbps. Illustrates the effect of setting the Auxiliary and direct interfaces write latency cycle(s) parameter to the value of four.


Figure 30. AUX TX Timing Diagram with Error

Illustrates the behavior of the aux_tx_err signal on the AUX TX interface of a CPRI IP core running at 0.6144 Gbps. The aux_tx_ctrl signal shows that when aux_tx_seq has the value of zero, the first byte at the corresponding position in the target CPRI frame is a control byte. The value of the Auxiliary and direct interfaces write latency cycle(s) parameter is zero. Therefore, the data on aux_tx_data is delayed by one clock cycle from the value on aux_tx_seq. The data that appears on aux_tx_data when aux_tx_seq has the value of 1 is the data that targets position X.Y.Z.0 in the target CPRI frame.

The value of Mask #1 is presumably 0xFFXXXXXX, indicating that the incoming data on aux_tx_data is intended to overwrite this control byte in the target CPRI frame. Therefore, in the following cpri_clkout cycle, the IP core asserts the aux_tx_err signal.



Related Information
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