CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
5. CPRI Intel® FPGA IP Core Registers x
5.1. INTR Register 5.2. L1_STATUS Register 5.3. L1_CONFIG Register 5.4. BIT_RATE_CONFIG Register 5.5. PROT_VER Register 5.6. TX_SCR Register 5.7. RX_SCR Register 5.8. CM_CONFIG Register 5.9. CM_STATUS Register 5.10. START_UP_SEQ Register 5.11. START_UP_TIMER Register 5.12. FLSAR Register 5.13. CTRL_INDEX Register 5.14. TX_CTRL Register 5.15. RX_CTRL Register 5.16. RX_ERR Register 5.17. RX_BFN Register 5.18. LOOPBACK Register 5.19. TX_DELAY Register 5.20. RX_DELAY Register 5.21. TX_EX_DELAY Register 5.22. RX_EX_DELAY Register 5.23. ROUND_TRIP_DELAY Register 5.24. XCVR_BITSLIP Register 5.25. DELAY_CAL_STD_CTRL1 Register 5.26. DELAY_CAL_STD_CTRL2 Register 5.27. DELAY_CAL_STD_CTRL3 Register 5.28. DELAY_CAL_STD_CTRL4 Register 5.29. DELAY_CAL_STD_CTRL5 Register 5.30. DELAY_CAL_STD_STATUS Register 5.31. DELAY_CAL_RTD Register 5.32. XCVR_TX_FIFO_DELAY Register 5.33. XCVR_RX_FIFO_DELAY Register 5.34. IP_INFO Register 5.35. DEBUG_STATUS Register
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.04.04 21.4 19.4.2
  • Added 1.2288G CPRI Line Bit Rate support for Intel® Agilex™ F-tile devices.
  • Updated the Device Family Support.
  • Updated steps in the following sections:
    • Understanding the Testbench
    • Running the Design Example
    • Writing the Hyperframe Control Words
  • Corrected the value on reset for:
    • rx_los
    • local_lof
    • local_los
    • rx_byte_delay
2021.11.11 21.2 19.4.0
  • Added the resource utilization for Intel® Agilex™ Device (with F-tile Transceivers).
  • Added additional information for Intel® Agilex™ F-tile devices in the following sections:
    • Generating CPRI Intel FPGA IP Cores
    • CPRI Intel FPGA IP File Structure
    • Running the Testbench
  • Added new parameter: Generate example design for (ED_TYPE)
  • Added clarifying information in sections:
    • Media Independent Interface (MII) to External Ethernet Block
    • Gigabit Media Independent Interface (GMII) to External Ethernet Block
2021.06.07 21.1 19.4.0
  • Added support for the Intel® Agilex™ F-tile devices.
  • Added new parameter: Enable resynchronization of CPRI radio frame number to desired value
  • Added new signal: aux_bfn_resync_value [11:0].
  • Update information on state machine transitions in section: Start-Up Sequence Following Reset.
  • Corrected the offset value for XCVR_RX_FIFO_DELAY Register and IP_INFO Register.
2021.03.05 20.4 19.3.0
  • Added support for the Intel® Agilex™ E-tile devices.
  • Corrected the following figures:
    • CPRI Master IP Core in External Clocking Mode for Intel® Stratix® 10 E- tile and Intel® Agilex™ E- tile Device Variations
    • CPRI Slave IP Core in External Clocking Mode for for Intel® Stratix® 10 E- tile and Intel® Agilex™ E- tile Device Variations
  • Added new resource utilization numbers for Intel® Agilex™ , Intel® Stratix® 10, and Intel® Arria® 10 using the Intel® Quartus® Prime Pro Edition software version 20.4.
  • Corrected the Figure: CPRI REC Master Response to aux_tx_sync_rfp Resynchronization Pulse.
  • Added clarification to the description of ROUND_TRIP_DELAY Register.
2020.10.27 19.2 19.2.0 Corrected the direction of the ehip_tx_pll_locked signal in Table: Transceiver and Transceiver Management Signals.
2020.09.25 19.2 19.2.0 Added GMII interface limitations in section Gigabit Media Independent Interface (GMII) to External Ethernet Block .
2019.10.01 19.2 19.2.0
  • The Intel® Stratix® 10 E-tile device support is now available for CPRI line rates 2.4575, 4.9152, 9.8304, 10.1376 and 24.33024 Gbps.
  • Clarified the slowest and highest speed grade support for the Intel® Stratix® 10 E-tile device.
  • Updated the resource utilization numbers for Intel® Stratix® 10 and Intel® Arria® 10 devices.
  • Added new parameters Transceiver tile to be used and Enable Reed-Solomon Forward Error Correction (RS-FEC) in Table: General CPRI Intel FPGA IP Core Parameters.
  • Updated Figure: Required External Blocks that includes the Intel® Stratix® 10 and V-series devices.
  • Added the TX PLL IP names for Intel® Stratix® 10 CPRI designs, updated TX PLL Signal names, and added information about E-tile designs in section Adding the Transceiver TX PLL IP Core.
  • Added new section Transceiver PLL Calibration.
  • Added the following new input clocks for Intel® Stratix® 10 E-tile device variations in Table: CPRI Intel FPGA IP Core Input Clocks:
    • pll_refclk0
    • pll_refclk
    • ehip_clk_403
    • ehip_clk_806
    • ehip_ref_clk[1:0]
  • Updated cpri_coreclk and cpri_clkout frequency values for Intel® Stratix® 10 E-tile designs.
  • Added new clock connections diagrams specific to Intel® Stratix® 10 E-tile device variations in Example CPRI Intel FPGA IP Core Clock Connections in Different Clocking Modes.
  • Added reset signal ehip_rst_n specific to Intel® Stratix® 10 E-tile device variations in Table: CPRI Intel FPGA IP Core Reset Signals.
  • Added new example Control Word Retrieval Example when Data path width is set to 64 in section Retrieving the Hyperframe Control Words.
  • Added new example Control Word Writing Example when Data path width is set to 64 in section Writing the Hyperframe Control Words.
  • Added reconfig_readdata_valid signal in Table: CPRI Intel FPGA IP Core Transceiver Reconfiguration Interface Signals.
  • Added ehip_tx_pll_locked signal in Table: Transceiver and Transceiver Management Signals.
  • Added new Figure: Address Map for Intel® Stratix® 10 E-tile Device Variations.
  • Updated CTRL_INDEX Register topic to include 64-bit interface information.
  • Added new register DEBUG_STATUS in Table: Control and Status Register Map.
2019.05.17 18.1 18.1
  • Renamed the document title as CPRI Intel® FPGA IP User Guide.
  • Changed the name of the IP to CPRI Intel FPGA IP in Intel® Quartus® Prime IP Catalog.
  • Renamed the IP parameter from Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
  • Clarified the generation method for the testbench and design example in section Understanding the Testbench.
  • Clarified the IP core variation file name in Intel® Quartus® Prime Standard Edition software.
  • Added new register IP_INFO in Table: Control and Status Register Map.
  • Added new register bit tx_scr_active in section TX_SCR Register.
  • Modified input clock name in Table: CPRI IP Core Input Clocks.
  • Corrected the equation of index X of a control word in section Specifying the Control Word.
  • Updated for latest Intel® branding standards.
2019.02.06 17.1 17.1 Changed the pdf filename from ug_cpri_70.pdf to ug_cpri.pdf
2019.01.28 17.1 17.1
  • Added support for Intel® Stratix® 10 devices with H- and L-tile transceivers.
  • Intel® Stratix® 10 device support is now available in 17.1 Intel® Quartus® Prime Pro Edition software.
  • Added Intel® Stratix® 10 device family support for new CPRI line bit rates of 12.16512 and 24.33024 Gbps.
  • Updated release information and resource utilization numbers for the 17.1 software release.
  • Added new parameter Data path width in Table: General CPRI Intel® FPGA IP Parameters.
  • Added new hybrid core clock source input.
  • Enable line bit rate auto-negotiation parameter is now available for Intel Stratix 10 and Intel Arria 10 devices.
  • Modified Running the Testbench section.
  • Added cpri_clkout frequency value for 12.16512 and 24.33024 Gbps CPRI line rates.
  • Clarified the value of xcvr_recovered_clk for different CPRI line bit rates.
  • Added new diagrams Figure: CPRI Master Intel® FPGA IP Core in Internal Clocking Mode and Figure: CPRI Slave Intel® FPGA IP Core in Internal Clocking Mode.
  • Modified the width of the signal auxN_rx_seq[6:0].
  • Changed the encoding values for all the CPRI line rates.
  • Modified signal names in following sections:
    • AUX Interface
    • Direct IQ Interface
    • ctrl_AxC Interface
    • Direct Vendor Specific Access Interface
    • Real-Time Vendor Specific Interface
Table 90.  Document Revision History

Date

Compatible ACDS Version

Changes

2018.01.04 17.0 IR3, 17.0, 17.0 Update 1, and 17.0 Update 2
  • Updated for the 17.0 software release, including Intel rebranding. Refer to Installation and Licensing, Generating CPRI Intel FPGA IP Core, and CPRI Intel FPGA IP File Structure.
  • Added Stratix 10 device family support for CPRI line bit rates of 1.2288 Gbps through 10.1376 Gbps. Because Stratix 10 device support is not available in the Intel® Quartus® Prime Pro Edition releases v17.0, v17.0 Update 1, and v17.0 Update 2, this version of the Intel® FPGA IP core provides Stratix 10 device support only in the Intel® Quartus® Prime Pro Edition software v17.0 IR3. Auto-rate negotiation and simplex modes are not yet available for CPRI Intel® FPGA IP core variations that target a Stratix 10 device.

  • Updated speed grade support table in CPRI Intel FPGA IP Core Performance: Device and Transceiver Speed Grade Support.

    • Added Stratix 10 support.
    • Added previously missing speed grade information for Arria V GZ devices at CPRI line rate 9.8304 Gbps.
    • Removed Arria 10 support for the CPRI line rate of 0.6144 Gbps. In the 17.0.260 release, the Intel® FPGA IP core no longer supports the CPRI line rate of 0.6144 Gbps for Arria 10 devices.
    • Corrected entries for Arria V GT and Cyclone V GT devices. The previous entries listed speed grades that do not exist for these devices.
  • Updated Intel® FPGA IP core parameters. Refer to CPRI Intel FPGA IP Core Parameters.
    • Updated default value of Line bit rate parameter. Intel® Arria® 10 and Intel® Stratix® 10 devices do not support the CPRI line bit rate of 0.6144 Gbps. The new default value is the lowest CPRI line bit rate the target device family supports: 1228.8 Mbps for Intel® Arria® 10 and Intel® Stratix® 10 device families; 614.4 Mbps (as before) for all other supported device families.
    • Specified the Intel® Stratix® 10 device family supports only TX/RX Duplex operation mode in the 17.0.260 release.
    • Moved Core clock source input parameter before Transmitter local clock division factor parameter.
    • Specified that Intel® FPGA IP core variations that target an Intel® Arria® 10 or Intel® Stratix® 10 device, with Line bit rate set to the value of 4915.2 Mbps or lower, support only the value of 1 for the Transmitter local clock division factor parameter. This change is new in the 17.0.260 release.
    • Specified that Intel® FPGA IP core variations that target a device family other than the Stratix V device family, support only the value of 1 for the Number of receiver CDR reference clock(s) parameter.
    • Added new VCCR_GXB and VCCT_GXB supply voltage for the transceiver parameter. This parameter affects the Intel® FPGA IP core only if it targets an Intel® Stratix® 10 device.
    • Specified the Recovered clock source parameter is not available for Intel® Arria® 10 and Intel® Stratix® 10 devices. Intel® FPGA IP cores that target either of these device families, support only a PCS clock source for the xcvr_recovered_clk.
    • Specified the Enable single-trip delay calibration parameter is only available for Intel® Arria® 10 devices.
    • Specified the Enable line bit rate auto-negotiation parameter is not available for Intel® FPGA IP core variations that target an Intel® Stratix® 10 device.

  • Added information about extended delay measurement for new Stratix 10 hard FIFOs. Refer to Extended Delay Measurement and the new section Extended Delay Measurement for Intel Stratix 10 Hard FIFOs. The new feature adds the following new parameters and registers:

  • Added new local_lof, local_los, lof_detected, and los_detected fields to the FLSAR register at offset 0x2C. This addition is new in the 16.1.275 release of the Intel® FPGA IP core. Added relevant information to descriptions of associated direct L1 control and status interface signals. Refer to FLSAR Register and to Direct L1 Control and Status Interface.
  • Added new section to clarify the conditions for transitions out of State G in the start-up sequence state machine. Refer to Start-Up Sequence Following Reset.
  • Renamed the old Start-Up Sequence Following Reset section to Start-Up Sequence Interface Signals. Corrected waveform in this section.
  • Added example waveforms for CPU interface and transceiver reconfiguration interface. Refer to CPU Interface Signals and Intel Arria 10, Intel Stratix 10, and Intel Agilex Transceiver Reconfiguration Interface.
  • Added Ctrl_AxC Interface section to document the signals and behavior on this interface. This information was previously missing.
  • Added L1 Debug Interface section to document the signals on this interface. This information was previously missing.
  • Corrected statement that the transceiver debug signals are available if you turn on Enable debug interface in the CPRI Intel® FPGA IP core parameter editor. The name of the parameter is Enable L1 debug interfaces.
  • Corrected TX MII timing diagram in Media Independent Interface (MII) to External Ethernet Block by removing extraneous HALT symbol (/F/).
  • Clarified that external Ethernet block must assert the mii_txen signal two cycles before it presents valid data on mii_txd[3:0], to allow the Intel® FPGA IP core to insert the /J/ and /K/ nibbles in outgoing CPRI communication to indicate start-of-packet. Refer to Media Independent Interface (MII) to External Ethernet Block.
  • Corrected GMII example waveforms in Gigabit Media Independent Interface (GMII) to External Ethernet Block. Control symbol is /V/ not /FE/, and the value of the symbol is 0x0E, not 0xFE. Also corrected text in section where appropriate.
  • Corrected rows for register DELAY_CAL_STD_CTRL2 and below in Control and Status Register Map table in CPRI Intel FPGA IP Core Registers. Offsets for these registers were already correct in sections for individual registers, but were listed incorrectly in the Control and Status Register Map table.
  • Clarified that the value in the startup_timer_period field of the START_UP_TIMER register at offset 0x28 is the number of cpri_coreclk clock cycles to the threshold. Refer to START_UP_TIMER Register.
  • Clarified that the value of the cal_rtd_ctrl field in the DELAY_CAL_RTD register at offset 0x80 is one-hot encoded.
  • Clarified origin of accepted HDLC and Ethernet rates. Refer to CM_STATUS Register.
  • Clarified that when the cal_tx_delay_usr_en field of the DELAY_CAL_STD_CTRL5 register at offset 0x70 has the value of 1, this value overrides the cal_rcv_en field in the DELAY_CAL_STD_CTRL4 register at offset 0x6C. Refer to DELAY_CAL_STD_CTRL4 Register and DELAY_CAL_STD_CTRL5 Register.
  • Filled in field names for tx_ctrl_seq and tx_ctrl_x fields of CTRL_INDEX register at offset 0x30, which were previously missing. Refer to CTRL_INDEX Register.
  • Corrected direction of rx_ready and tx_ready output signals from reset controller. Refer to Adding the Reset Controller.
  • Added Compiling the Full Design and Programming the FPGA section in Getting Started chapter. This section provides the location of the Synopsys Design Constraints file (.sdc) generated with the Intel® FPGA IP core.
  • Removed How to Contact and Typographic Conventions sections.
  • Removed Differences Between CPRI Intel® FPGA IP Core and CPRI Intel® FPGA IP Core appendix. The CPRI Intel® FPGA IP core is not available for recent versions of the Intel® Quartus® Prime software.
  • Removed Installation and Licensing Features section, which described the OpenCore Plus feature. Because the CPRI Intel® FPGA IP core is available from the SSLC only with a license, this feature is not relevant.
  • Added new section with links to older published versions of this user guide. If a correction was published for the same software version, only the corrected version is available. Refer to CPRI Intel FPGA IP User Guide Archives.
  • Fixed assorted typos and minor errors.
2016.07.22 16.0
  • Updated for 16.0 software release. Updated release information and resource utilization numbers for the 16.0 software release.
  • Updated speed grade support table in CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support.
  • Added Arria 10 and Stratix V device family support for CPRI line bit rate of 8.11008 Gbps. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.258.
  • Removed Arria 10 device family support for CPRI line bit rate of 0.6144 Gbps. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.313.
  • Added support for single-trip delay calibration. This Intel® FPGA IP core change is new in the CPRI Intel® FPGA IP core release 16.0.
    • Added new parameters Core clock source input and Enable single-trip delay calibration. Refer to CPRI Intel® FPGA IP Core Parameters and Running the Testbench.
    • Added new clocking structure, new IOPLL and DPCU blocks, and new top-level signal tx_clkout. Refer to CPRI Intel® FPGA IP Core Clocking Structure, CPRI Intel® FPGA IP Core Management Interfaces, Adding the Off-Chip Clean-Up PLL, and new section Example CPRI Clock Connections in Different Clocking Modes.
    • Added new Intel® FPGA IP core signals cal_status[1:0] and cal_ctrl[15:0]. Refer to Adding and Connecting the Single-Trip Delay Calibration Blocks and Single-Trip Latency Measurement and Calibration Interface Signals.
    • Added new registers DELAY_CAL_STD_CTRL1, DELAY_CAL_STD_CTRL2, DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL4, DELAY_CAL_STD_CTRL5, and DELAY_CAL_STD_STATUS. Refer to CPRI Intel® FPGA IP Core Registers.
    • Added description of new features in new sections Delay Calibration Features and Single-trip Delay Calibration.
  • Added support for round-trip latency calibration. This Intel® FPGA IP core change is new in the CPRI Intel® FPGA IP core release 16.0.
    • Added new parameters Enable round-trip delay calibration and Round-trip delay calibration FIFO depth. Refer to CPRI Intel® FPGA IP Core Parameters and Running the Testbench.
    • Added new register DELAY_CAL_RTD. Refer to DELAY_CAL_RTD Register.
    • Added description of new features in new section Round-Trip Delay Calibration.
  • Added parameters to control Avalon-MM CPU interface addressing mode and to enable ADME support. Refer to CPRI Intel® FPGA IP Core Parameters. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.258.
    • Previously the CPU interface addressing mode was always word (4-byte) addressing mode. For CPU interface addressing mode changes, refer to CPU Interface to CPRI Intel® FPGA IP Core Registers and CPU Interface Signals.
    • You can turn on ADME support to support debugging through the Altera System Console and to expose transceiver registers. This parameter is available only in CPRI Intel® FPGA IP cores that target an Arria 10 device. For additional information about this parameter, refer to Arria 10 Transceiver Reconfiguration Interface.
  • The transceiver reconfiguration interface is no longer available in certain configurations of the CPRI Intel® FPGA IP core. Refer to CPRI Intel® FPGA IP Core Parameters, Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface and Arria 10 Transceiver Reconfiguration Interface. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.258.
  • The xcvr_rx_is_lockedtodata signal is now available whether or not you turn on Enable debug interface in the parameter editor. Refer to Transceiver Debug Interface and CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals. This Intel® FPGA IP core change is new in the CPRI Intel® FPGA IP core release 16.0.
  • Expanded width of round_trip_delay field in ROUND_TRIP_DELAY register from 10 bits to 20 bits. Refer to ROUND_TRIP_DELAY Register. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.313.
  • Added new top-level signals tx_analogreset_ack and rx_analogreset_ack. These signals are available in Arria 10 variations with Enable line bit rate auto-negotiation turned on. Refer to Auto-Rate Negotiation and CPRI Intel® FPGA IP Core Management Interfaces. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.258.
  • Changed name of cpri_10g_coreclk input clock signal to cpri_coreclk. Refer to CPRI Intel® FPGA IP Core Clocking Structure and CPRI Intel® FPGA IP Core Management Interfaces. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.258.
  • Removed xcvr_reset_tx and xcvr_reset_rx signals. Refer to Adding the Reset Controller and CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals.
  • Specified the Recovered clock source parameter is no longer available for CPRI master Intel® FPGA IP cores. This Intel® FPGA IP core change is new in the CPRI Intel® FPGA IP core release 16.0.
  • Specified the xcvr_recovered_clk output clock is available only in CPRI slave Intel® FPGA IP cores. Refer to CPRI Intel® FPGA IP Core Clocking Structure and Main Transceiver Clock and Reset Signals. This Intel® FPGA IP core change occurred in the CPRI Intel® FPGA IP core release 15.1.258.
  • Corrected direction of multiple Transceiver Reset Controller signals in Required Connections to and From Reset Controllers in CPRI Design table in Adding the Reset Controller.
  • Fixed assorted typos and minor errors.
2015.09.29 15.0
  • Corrected RX GMII Timing Diagram figure. Refer to Gigabit Media Independent Interface (GMII) to External Ethernet Block.
  • Clarified that the limitation of the testbench to CPRI line bit rates other than 614.4 Mbps only applies for Arria 10 devices. All other device families support a testbench for a DUT with the CPRI line bit rate of 614.4 Mbps. Refer to Running the Testbench.
2015.09.25 15.0
  • Changed document part number from UG-01156 to UG-20008. The document title is not affected.
  • Added support for Arria V GT, Arria V GX, Cyclone V GT, and Cyclone V GX devices.
  • Updated for 15.0 software release. Updated release information and resource utilization numbers for the 15.0 software release.
  • Modified device speed grade recommendations:
    • Added supported transceiver speed grade information.
    • Added device and transceiver speed grade support information for the previously unsupported device families.
  • Added support for new GMII interface to external Ethernet block. Refer to Gigabit Media Independent Interface (GMII) to External Ethernet Block.
  • Expanded Deterministic Latency and Delay Measurement and Calibration section. Removed latency numbers and examples, which are now available on the Altera wiki.
  • Updated Intel® FPGA IP core parameters. Refer to CPRI Intel® FPGA IP Core Parameters.
    • Added new Operation mode parameter. This parameter determines whether the Intel® FPGA IP core is in TX simplex, RX simplex, or duplex mode. Note the old Operation mode parameter from previous releases is renamed .
    • Renamed the old Operation mode parameter to Synchronization mode. This parameter determines the default clocking mode of the Intel® FPGA IP core (Master or Slave clocking mode). Unfortunately, the operation_mode field of the LI_CONFIG register is not renamed. This field supports dynamic reconfiguration of the Intel® FPGA IP core clocking mode. Refer to L1_CONFIG Register.
    • Added new Transmitter local clock division factor parameter. This parameter enables you to include multiple instances of the CPRI Intel® FPGA IP core with different CPRI line bit rates using the same external transceiver TX PLL.
    • Added new Number of receiver CDR reference clock(s) parameter. This parameter supports Stratix V variations in auto-negotiation to or from the CPRI line bit rate of 10.1376 Gbps.
    • Added new Recovered clock source parameter. This parameter supports auto-negotiation in Stratix V variations to or from the CPRI line bit rate of 10.1376 Gbps.
    • Changed name of Bit rate (Mbit/s) parameter to Line bit rate (MBit/s). Enhanced description to include new supported devices.
    • Changed name of Supported receiver CDR frequency (MHz) parameter to Receiver CDR reference clock frequency (MHz).
    • Changed name of Receiver FIFO depth parameter to Receiver soft buffer depth.
    • Changed name of Enable auto-rate negotiation parameter to Enable line bit rate auto-negotiation.
    • Changed name of Enable auto-rate negotiation down to 614.4 Mbps parameter to Enable line bit rate auto-negotiation down to 614.4 Mbps.
    • Changed name of Supported CPU interface standard parameter to Management (CSR) interface standard.
    • Changed name of Auxiliary latency cycle(s) parameter to Auxiliary and direct interfaces write latency cycle(s).
    • Changed name of Enable all control word access parameter to Enable all control word access via management interface.
    • Changed name of Enable Z.130.0 access interface parameter to Enable direct Z.130.0 alarm bits access interface.
    • Changed name of Enable real-time vendor specific interface (R-16A) parameter to Enable direct real-time vendor specific interface .
    • Changed name of Enable L1 inband protocol negotiator parameter to Enable protocol version and C&M channel setting auto-negotiation.
    • Changed order of some L1 Feature parameters to reflect their new order in the CPRI parameter editor.
    • Changed name of Enable direct HDLC serial interface parameter to Enable HDLC serial interface.
    • Changed name of Enable IEEE 802.3 100BASE-X 100Mbps MII On/Off parameter to Ethernet PCS interface multi-value parameter, and added new parameter value GMII. The On/Off parameter supported the values "None" and "MII", which are still available.
    • Added allowed value of 11 for L2 Ethernet PCS Tx/Rx FIFO depth parameter, increasing the maximum L2 Ethernet buffer depth to 2048.
    • Changed names of loopback-enable parameters to include "serial" or "parallel."
  • Appended "_n" to names of active low reset signals.
  • Modified recommended reset connections and added four new Intel® FPGA IP core reset signals: reset_tx_n, reset_rx_n, xcvr_reset_tx, and xcvr_reset_rx.
  • Fixed assorted typos and minor errors.

2015.02.16

14.0 and 14.0 Arria 10 Edition

  • Corrected name of ROUND_TRIP_DELAY register at offset 0x058. The register name was previously listed incorrectly as ROUND_DELAY.
  • Corrected names of rx_hfnsync and rx_hfnsync_hold fields of L1_STATUS register at offset 0x04. The fields were previously listed incorrectly as rx_state and rx_state_hold.
  • Fixed assorted typos.
Note: This version of the user guide documents the same Intel® FPGA IP core version that the 2014.08.18 user guide documents.

2014.08.18

14.0 and 14.0 Arria 10 Edition

Initial release for Arria 10 device support. Corrected multiple figures associated with the AUX interface synchronization signals and the Auxiliary latency cycle(s) parameter. Added discussion of external clean-up PLL in Getting Started chapter. Added multiple sections to Functional Description chapter, including section on latency. Added resource utilization numbers. Moved detailed signal descriptions into relevant sections in Functional Description chapter; the Signals chapter is now a port listing summary. Corrected assorted errors and typos.

2014.07.28

14.0

Preliminary restricted document release.

Level Two Title