CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
5. CPRI Intel® FPGA IP Core Registers x
5.1. INTR Register 5.2. L1_STATUS Register 5.3. L1_CONFIG Register 5.4. BIT_RATE_CONFIG Register 5.5. PROT_VER Register 5.6. TX_SCR Register 5.7. RX_SCR Register 5.8. CM_CONFIG Register 5.9. CM_STATUS Register 5.10. START_UP_SEQ Register 5.11. START_UP_TIMER Register 5.12. FLSAR Register 5.13. CTRL_INDEX Register 5.14. TX_CTRL Register 5.15. RX_CTRL Register 5.16. RX_ERR Register 5.17. RX_BFN Register 5.18. LOOPBACK Register 5.19. TX_DELAY Register 5.20. RX_DELAY Register 5.21. TX_EX_DELAY Register 5.22. RX_EX_DELAY Register 5.23. ROUND_TRIP_DELAY Register 5.24. XCVR_BITSLIP Register 5.25. DELAY_CAL_STD_CTRL1 Register 5.26. DELAY_CAL_STD_CTRL2 Register 5.27. DELAY_CAL_STD_CTRL3 Register 5.28. DELAY_CAL_STD_CTRL4 Register 5.29. DELAY_CAL_STD_CTRL5 Register 5.30. DELAY_CAL_STD_STATUS Register 5.31. DELAY_CAL_RTD Register 5.32. XCVR_TX_FIFO_DELAY Register 5.33. XCVR_RX_FIFO_DELAY Register 5.34. IP_INFO Register 5.35. DEBUG_STATUS Register
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

2.4. CPRI Intel® FPGA IP Core Parameters

The CPRI parameter editor provides the parameters you can set to configure the CPRI IP core and simulation testbench.

The CPRI parameter editor has four tabs:
  • General
  • Interfaces
  • Advanced
  • Simulation
Table 9.  General CPRI Intel® FPGA IP Core ParametersDescribes the general parameters for customizing the CPRI IP core. These parameters appear on the General tab in the CPRI parameter editor.

Parameter

Options

Default Setting

Parameter Description

Selected device family

(DEVICE_FAMILY)

  • Intel® Agilex™
  • Intel® Stratix® 10
  • Intel® Arria® 10
  • Stratix® V
  • Arria® V
  • Cyclone® V
- Specifies the target device.
Transceiver tile to be used

(GUI_TILE)
  • F
  • E
  • H
 E Selects the appropriate tile.

This parameter in only available in CPRI IP core variations that target an Intel® Stratix® 10 and Intel® Agilex™ device.

Line bit rate (Mbits/s)

(BIT_RATE)

  • 614.4
  • 1228.8
  • 2457.6
  • 3072.0
  • 4915.2
  • 6144.0
  • 8110.08
  • 9830.4
  • 10137.6
  • 12165.12
  • 24330.24

Lowest bit rate supported for the device family

Selects the CPRI line bit rate. Refer to CPRI Intel FPGA IP Core Performance: Device and Transceiver Speed Grade Support for supported CPRI line bit rates in the supported device families.

The parameter editor does not allow you to specify a CPRI line bit rate that the target device does not support.

Data path width

(CORE_WIDTH)
  • 32
  • 64
 32 This parameter specifies the parallel interface width.

CPRI IP core variations with line bit rate values of 10.1376, 12.16512 or 24.33024 Gbps set this parameter value to 64.

For all other device variations and combinations, this parameter value is 32.

Although value of this parameter is fixed and represents the active parallel interfaces corresponding to initial line bit rate, both 32-bit interface and 64-bit interface can coexist depending on the configuration.

If line bit rate auto-negotiation is turned off, only one interface width (32-bit/64-bit) exist which is indicated by this parameter.

If line bit rate auto-negotiation is turned on, you might exercise either 32-bit or 64-bit interface at a time.

Synchronization mode

(SYNC_MODE)
  • Master
  • Slave
Master

Specifies whether the CPRI IP core is configured as a CPRI link master or a CPRI link slave.

The value of this parameter determines the initial and reset clocking mode of the CPRI IP core. You can modify the IP core clocking mode dynamically by modifying the value of the synchronization_mode field of the L1_CONFIG register.

Enable Reed-Solomon Forward Error Correction (RSFEC)

(EN_RSFEC)
  • True
  • False
 False This parameter specifies if the design includes the RS-FEC logic.

This parameter is only available in CPRI IP core variations that target an Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile device.

This option is grayed out and disabled in the current version of the Intel® Quartus® Prime software.

Operation mode

(TRX_MODE)

  • TX/RX Duplex
  • TX Simplex
  • RX Simplex
 TX/RX Duplex

Specifies whether the CPRI IP core is configured with RX functionality only (RX Simplex), with TX functionality only (TX Simplex), or with both RX and TX functionality (TX/TX Duplex).

If you specify a simplex mode, the Intel® Quartus® Prime Fitter synthesizes logic for only one direction of traffic. In the TX simplex mode, it can transmit traffic on the CPRI link but cannot receive. In the RX simplex mode, it can receive traffic on the CPRI link but cannot transmit.

Core clock source input

(CORE_CLK_SRC)
  • External
  • Internal
  • Hybrid
Internal Specifies the clock source of the cpri_clkout port that drives the core.

The external clocking scheme supports the single-trip delay calibration feature. In this clocking scheme, the clock fed from cpri_coreclk drives the cpri_clkout at all CPRI line bit rates.

In the internal clocking scheme, the clock from the transceiver PHY drives the cpri_clkout.

The hybrid option is available only when you select at least one CPRI line bit rate from Group 1 and Group 2 of the table below and enable line bit rate auto-negotiation parameter:
Group 1 (Gbps) Group 2 (Gbps)
0.6144, 1.2288, 2.4576, 3.072, 4.9152, 6.1440, 9.8304 8.11008, 10.1376, 12.16512, 24.33024

In hybrid mode, the Intel® FPGA IP works in the Internal clocking scheme when you select CPRI line bit rates from Group 1 and works in external mode clocking scheme when you select the CPRI line bit rates from Group 2.

For Intel Intel® Arria® 10 device and Intel Intel® Stratix® 10 L/H-Tile device, the line bit rate 8.11008 Gbps and 10.1376 Gbps do not support Internal clocking mode.

The hybrid clocking mode option is not available in IP core variations that target an Intel® Stratix® 10 or Intel® Agilex™ E-tile device.

Transmitter local clock division factor

(TX_LOCAL_CLK_DIV)
  • 1
  • 2
  • 4
  • 8
 1 Specifies the division factor for the local clock divider. The IP core divides the high speed clock from the transceiver TX PLL (xcvr_ext_pll_clk) to generate the serial TX clock.

This feature supports the configuration of multiple instances of the CPRI IP core that run at different CPRI line bit rates but share use of the same TX PLL.

This parameter is not available if you set the value of Operation mode to RX Simplex.

IP core variations that target an Intel® Arria® 10 device or Intel® Stratix® 10 or Intel® Agilex™ device, with Line bit rate set to 4915.2 Mbps or slower, support only the value of 1.

Number of receiver CDR reference clock(s)

(CDR_REFCLK_CNT)
  • 1
  • 2
 1 Specifies the number of reference clocks that can feed the receiver. The CPRI IP core supports the selection of one or two clocks. This option supports auto-negotiation to and from the CPRI line bit rate of 10.1376 Gbps in CPRI IP core variations that target a Stratix V device. Refer to IP Core Clocking Structure.

If you set this parameter to the value of 1, the xcvr_cdr_refclk is a single clock. If you set this parameter to the value of 2, the xcvr_cdr_refclk input signal is two bits wide, to support two distinct reference clocks.

Intel® recommends that you specify a two-bit CDR reference clock for Stratix V variations that are expected to implement auto-negotiation up to a 10.1376 Gbps CPRI line bit rate. For example, one bit of the xcvr_cdr_refclk clock with a common 307.2 MHz clock for the lower CPRI line bit rates and drives the other bit with a 253.44 MHz clock for the 10.1376 Gbps CPRI line bit rate.

If the value of this parameter is 2, the receiver clocks the CDR with the xcvr_cdr_refclk[0] input signal by default. You can switch the receiver to use xcvr_cdr_refclk[1], or back to xcvr_cdr_refclk[0], by dynamically reconfiguring the RX transceiver.

CPRI IP core variations that target Stratix V device family, support only a single-bit CDR reference clock.

CPRI IP core variations that target an Intel® Arria® 10 or Intel® Stratix® 10 or Intel® Agilex™ device family, support single and two bit receiver CDR reference clock in the following conditions:
  • Intel® Arria® 10 devices with auto-rate negotiation on and with the CPRI line bit rate is 8.11008 Gbps or greater.
  • Intel® Stratix® 10 devices with auto-rate negotiation option on.
  • Intel® Agilex™ devices with auto-rate negotiation option on.
For all other cases, set this parameter value to 1.

This parameter is not available if you set the value of Operation mode to TX Simplex.

Receiver CDR reference clock frequency (MHz)

(CDR_XCVR_FREQ)

 Per drop-down menu 307.2

Specifies the incoming reference clock frequency for the receiver CDR PLL, in MHz.

You must drive the input clock xcvr_cdr_refclk or xcvr_cdr_refclk[0] at the frequency you specify for this parameter.

This parameter is not available if you set the value of Operation mode to TX Simplex.

VCCR_GXB and VCCT_GXB supply voltage for the transceiver

(XCVR_ANLG_VOLTAGE)
  • 1_1V
  • 1_0V
 1_1V Specifies whether the transceiver supply voltage is 1.1 V or 1.0 V. The supply voltage must match the voltage you specify for this parameter, in IP core variations that target an Intel® Stratix® 10 or Intel® Agilex™ device.

This parameter affects only IP core variations that target an Intel® Stratix® 10 or Intel® Agilex™ device. You can ignore it for other device families.

Recovered clock source

(RCVD_CLK)
  • PCS
  • PMA
 PCS Specifies the clock source of the xcvr_recovered_clk.

Intel® recommends that you set this parameter to the value of PMA in IP core variations that target a Stratix V device, if you expect your IP core to auto-negotiate to or from the CPRI line bit rate of 10.1376 Gbps. In this case, sourcing the recovered clock from the PMA improves jitter on that clock. If you specify the PCS source, the IP core switches between two PCS-internal clocks at auto-negotiation to or from the CPRI line bit rate of 10.1376 Gbps.

This parameter is not available for
  • CPRI master IP cores
  • IP cores that target an Intel® Agilex™ or Intel® Stratix® 10 or Intel® Arria® 10 device
  • IP cores for which you set the value of Operation mode to TX Simplex
Receiver soft buffer depth

(WIDTH_RX_BUF)

4, 5, 6, 7, or 8 6

The value you specify for this parameter is log2 of the IP core Layer 1 Rx buffer depth.The IP core supports a maximum Layer 1 RX buffer depth of 256.

The default depth of the buffer is 64, specified by the parameter default value of 6. For most systems, the default buffer depth is adequate to handle dispersion, jitter, and drift that can occur on the link while the system is running. However, the parameter is available for cases in which additional depth is required.

Increasing the value of this parameter increases resource utilization. Increasing the value of this parameter affects latency only when the buffer fills beyond the default capacity. In that case, the larger buffer increases latency but prevents data loss.

The user guide refers to this parameter value as RX_BUF_DEPTH.

This parameter is not available if you set the value of Operation mode to TX Simplex.

Transmit soft buffer depth

(TX_BUF_WIDTH)

 4, 5, 6, 7, or 8 4 The value you specify for this parameter is log2 of the IP core Layer 1 TX buffer depth. The IP core supports a maximum Layer 1 TX buffer depth of 256.

This parameter is not available if you set the value of Operation mode to RX Simplex.

Enable line bit rate auto-negotiation

(AUTORATE)

  • On
  • Off
Off

Turn on the Enable line bit rate auto-negotiation parameter to specify that your CPRI IP core supports auto-rate negotiation.

If you turn on this parameter, your IP core does not implement auto-negotiation. You must dynamically reconfigure the transceiver PHY to modify the CPRI line bit rate and implement auto-negotiation. However, if you turn off this parameter, the IP core does not support bit line rate auto-negotiation, and you cannot modify the CPRI line bit rate dynamically.

If you turn off this parameter and also turn off Enable start-up sequence state machine, and in Intel® Arria® 10, Intel® Agilex™ , and Intel® Stratix® 10 devices, the Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access, the transceiver reconfiguration interface is not available.

This parameter is only available for Intel® Arria® 10, Intel® Agilex™ , and Intel® Stratix® 10 devices when you specify a CPRI line bit rate (value for the Line bit rate parameter) that is greater than 1228.8 Mbps.

614.4 Mbit/s

(RATE614)
  • On
  • Off
Off These options are available when you turn on Enable line bit rate auto-negotiation parameter. You must select a CPRI line bit rate (value of the Line bit rate (Mbit/s) parameter) that is greater than one or more line bit rate (s) which you would like to negotiate to.

You must choose at least two or more CPRI line bit rates to rate negotiate to if you turn on line bit rate auto-negotiation.

1228.8 Mbit/s

(RATE1228)
2457.6 Mbit/s

(RATE2457)
3072.0 Mbit/s

(RATE3072)
4915.2 Mbit/s

(RATE4915)
6144.0 Mbit/s

(RATE6144)
8110.08 Mbit/s

(RATE8110)
9830.4 Mbit/s

(RATE9830)
10137.6 Mbit/s

(RATE10137)
12165.12 Mbit/s

(RATE12165)
Table 10.   CPRI Intel® FPGA IP Core Interface Feature ParametersDescribes the parameters for customizing the CPRI IP core Layer 1 and Layer 2 interfaces and testing features. These parameters appear on the Interfaces tab in the CPRI parameter editor.

Parameter

Options

Default Setting

Parameter Description

L1 Features
Management (CSR) interface standard

(CPU_IF_MODE)

Currently, only the Avalon-MM CPU interface is available in the CPRI IP core.

Selects the interface specification that describes the behavior of the CPRI IP core register access interface.

Avalon-MM interface addressing type

(CPU_IF_ADDR_MODE)
  • Word
  • Byte
 Word Specifies the addressing mode for the Avalon-MM CPU interface. If the addressing mode is Word, you must ensure you correctly align the connections between Avalon-MM components. This parameter specifies how other components must connect to the cpu_address bus on the CPU interface.
Auxiliary and direct interfaces write latency cycle(s)

(IF_LATENCY)

0 to 9 0

Specifies the additional write latency on the AUX TX interface and other direct TX interfaces to the CPRI IP core. The write latency is the number of cpri_clkout cycles from when the aux_tx_seq output signal has the value of 0 to when user logic writes data to the AUX TX interface. For other direct interfaces, the IP core notifies user logic when it is ready for input and the user does not need to monitor the aux_tx_seq signal.

When Auxiliary and direct interfaces write latency cycle(s) has the value of zero, the write latency on the direct TX interfaces is one cpri_clkout cycle. When Auxiliary and direct interfaces write latency cycle(s) has the value of N, the write latency is (1+N) cpri_clkout cycles.

Set this parameter to a value that provides user logic with sufficient advance notice of the position in the CPRI frame. The processing time that user logic requires after determining the current position in the CPRI frame is implementation specific.

This parameter is available if you turn on at least one direct interface in your CPRI IP core variation.

Enable auxiliary interface

(AUX_EN)

  • On
  • Off
Off

Turn on this parameter to include the AUX interface in your CPRI IP core. The AUX interface provides full access to the raw CPRI frame.

Enable all control word access via management interface

(CPU_CTRL_WD_EN)

  • On
  • Off
Off

Turn on this parameter to enable access to all control words in a hyperframe using the CPRI CTRL_INDEX, TX_CTRL, and RX_CTRL registers.

Use this option with caution. During transmission, this feature has higher priority than the MII, the GMII, the HDLC serial interface, the L1 control and status interface, and the generation of special symbols (K28.5, D16.2, /S/, /T/) , and can overwrite standard control words in the hyperframe.

Enable direct Z.130.0 alarm bits access interface

(FLSAR_EN)

  • On
  • Off
Off

Turn on this parameter to include a dedicated L1 control and status interface to communicate the contents of the CPRI frame Z.130.0 word, which includes alarms and reset signals.

Enable direct ctrl_axc access interface

(CTRL_AXC_EN)

  • On
  • Off
Off

Turn on this parameter to include a dedicated interface to access the Ctrl_AxC subchannels in the CPRI frame.

Enable direct vendor specific access interface

(VS_EN)

  • On
  • Off
Off

Turn on this parameter to include a dedicated interface to access the VS subchannels in the CPRI frame.

Enable direct real-time vendor specific interface

(RTVS_EN)

  • On
  • Off
Off

Turn on this parameter to include a dedicated interface to access the RTVS subchannel in the CPRI frame.

This parameter is available when you specify a CPRI line bit rate of 10137.6 Mbps.

Enable resynchronization of CPRI radio frame number to desired value

(BFN_RESYNC_EN)
  • On
  • Off
Off This parameter is for resynchronization of outgoing CPRI radio frame number with nodeB Frame Number (BFN). If turned on, you may use a dedicated port to specify 12-bit value which takes effect on next clock cyle after positive edge of auxN_tx_sync_rfp. If turned off, upon assertion of auxN_tx_sync_rfp, outgoing CPRI radio frame number is incremented.
Enable start-up sequence state machine

(STARTUP_SEQ_SM_EN)

  • On
  • Off
Off

Turn on this parameter to include a start-up sequence state machine in the CPRI IP core.

If you turn off this parameter and also turn off Enable line bit rate auto-negotiation, Enable single-trip delay calibration, and in Intel® Arria® 10 and Intel® Stratix® 10 devices, the Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access, the transceiver reconfiguration interface is not available.

This parameter is available if you set the value of Operation mode to TX/RX Duplex.

Note: If you disable this parameter, you cannot calibrate your transceiver PHY.
Enable protocol version and C&M channel setting auto-negotiation

(NEGO_EN)

  • On
  • Off
Off

Turn on this parameter to include a negotiator block that performs auto-negotiation of L1 inband protocol version (communicated in CPRI frame position Z.2.0) and L2 C&M rates (communicated in CPRI frame positions Z.66.0 and Z.194.0).

This parameter is available when you turn on Enable start-up sequence state machine.

Enable direct I/Q mapping interface

(IQ_EN)

  • On
  • Off
Off

Turn on this parameter to include a dedicated interface to access the raw I/Q data bytes in the CPRI frame.

L2 Features
Enable HDLC serial interface

(HDLC_SERIAL_EN)

  • On
  • Off
Off

Turn on this parameter to include a dedicated interface to communicate the contents of the slow C&M subchannels.

For full HDLC communication, you must connect a user-defined HDLC module to this interface.

Ethernet PCS interface

(XMI_IF_EN)

  • NONE
  • MII
  • GMII
 NONE

Specify whether to include an MII or GMII port to communicate with the fast C&M (Ethernet) CPRI subchannel. You can also specify that the IP core does not support either interface.

  • An MII port complies with the IEEE 802.3 100BASE-X 100Mbps MII specification,
  • A GMII port complies with the IEEE 802.3 1000BASE-X 1Gbps GMII specification.

For full Ethernet communication, you must connect a user-defined Ethernet MAC to this interface.

GMII option is not available for CPRI IP core variations that target Intel® Stratix® 10 device with line bit rate value 12165.12 or 24330.24 Mbps.
L2 Ethernet PCS Tx/Rx buffer depth

(ETH_PCS_BUF_WIDTH)

7, 8, 9, 10, 11 7

The value you specify for this parameter is log2 of the IP core Layer 2 Ethernet PCS Rx buffer depth and Tx buffer depth. The IP core supports a maximum Layer 2 Ethernet PCS buffer depth of 1024 for MII and 2048 for GMII.

This parameter is available when you include an MII or GMII port to communicate with the fast C&M (Ethernet) CPRI subchannel by selecting the value of MII or GMII for the Ethernet PCS interface parameter.

The new value of 11 is supported only for GMII.

Debug Features
Enable L1 debug interfaces

(DEBUG_EN)

  • On
  • Off
Off

Turn on this parameter to include dedicated transceiver status and L1 Rx status interfaces to support debug.

This parameter is not available if you set the value of Operation mode to TX Simplex.

Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access

(DEBUG_XCVR_EN)
  • On
  • Off
Off

Turn on this parameter to support debugging through the System Console and to expose transceiver registers. If you turn off this parameter and also turn off Enable line bit rate auto-negotiation, Enable start-up sequence state machine, and Enable single-trip delay calibration, the Intel® Arria® 10 or Intel® Stratix® 10 transceiver reconfiguration interface is not available.

This parameter is available only for Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: If you disable this parameter, you cannot calibrate your transceiver PHY.
Enable transceiver PMA serial forward loopback path

(DEBUG_SERIAL_LB_EN)

  • On
  • Off
Off

Turn on this parameter to enable transceiver PMA serial forward loopback. To turn on transceiver PMA serial forward loopback (Tx to Rx), you must also write the value of 2'b01 to the loop_forward field of the LOOPBACK register at offset 0x44.

This parameter is not available if you set the value of Operation mode to TX Simplex or to RX Simplex.

This parameter is not available for Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile devices. You can perform the transceiver PMA serial forward loopback in E-tile CPRI designs by writing directly to the PHY registers. Refer to the E-Tile Transceiver PHY User Guide for more information.

Enable parallel forward loopback paths

(DEBUG_FORWARD_LB_EN)

  • On
  • Off
Off

Turn on this parameter to enable other internal parallel forward loopback paths (Tx to Rx). To turn on internal parallel forward loopback, you must also write a non-zero value to the loop_forward field of the LOOPBACK register at offset 0x44.

This parameter is not available if you set the value of Operation mode to TX Simplex or to RX Simplex.

Enable parallel reversed loopback paths

(DEBUG_REVERSE_LB_EN)

  • On
  • Off
Off

Turn on this parameter to enable internal parallel reverse loopback (Rx to Tx). To turn on reverse loopback, you must also write a non-zero value to the loop_reversed field of the LOOPBACK register at offset 0x44, to specify the parts of the CPRI frame that are sent on the loopback path.

This parameter is not available if you set the value of Operation mode to TX Simplex or to RX Simplex.

Table 11.   CPRI Intel® FPGA IP Core Advanced Feature ParametersDescribes the parameters for customizing the CPRI IP core delay calibration features. These parameters appear on the Advanced tab in the CPRI parameter editor.

Parameter

Options

Default Setting

Parameter Description

Enable single-trip delay calibration

(CALEN)
  • On
  • Off
Off Turn on this parameter to specify that your CPRI IP core supports single-trip delay calibration.

If you turn on this parameter, your IP core implements single-trip delay calibration only if you connect it according to Adding and Connecting the Single-Trip Delay Calibration Blocks. Intel® provides the required external blocks but you must connect them to the IP core in your design.

This parameter is only available in IP core variations that target an Intel® Arria® 10 device.

If you turn off this parameter and also turn off Enable line bit rate auto-negotiation, Enable start-up sequence state machine the transceiver reconfiguration interface is not available.
Note: If you disable Enable line bit rate auto-negotiation parameter, you cannot calibrate your transceiver PHY.

This parameter is available only if you set the value of the Core clock source input parameter to External.

Enable round-trip delay calibration

(CAL_RTD_EN)
  • On
  • Off
Off Turn on this parameter to to specify that your CPRI IP core supports round-trip delay calibration.

This parameter is available only if you set the value of the Synchronization mode parameter to Master.

Round-trip delay calibration FIFO depth

(CAL_RTD_FIFO_DEPTH)
  • 2
  • 3
  • 4
 2

The value you specify for this parameter is log2 of the IP core RTD calibration buffer depth. The IP core supports a maximum RTD calibration buffer depth of 16.

The default depth of the buffer is 4, specified by the parameter default value of 2. For buffer depth N, the Read pointer can move (N/2)-1 entries in either direction from its initial state.

Generate example design for

(ED_TYPE)
  • synthesis and simulation
  • synthesis
  • simulation
 simulation

The value you specify for this parameter determines the type of example design to be generated.

Table 12.   CPRI Intel® FPGA IP Core Simulation ParametersDescribes the parameters for customizing the CPRI IP core delay calibration features. These parameters appear on the Advanced tab in the CPRI parameter editor.

Parameter

Options

Default Setting

Parameter Description

Language for top-level simulation file

(SIM_LANGUAGE)
  • Verilog
  • VHDL
 Verilog

This parameter determines the language of the top-level simulation file.

Related Information
Level Two Title