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2.1. Installation and Licensing
2.2. Generating CPRI Intel® FPGA IP Core
2.3. CPRI Intel® FPGA IP File Structure
2.4. CPRI Intel® FPGA IP Core Parameters
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks
2.6. Simulating Intel FPGA IP Cores
2.7. Understanding the Testbench
2.8. Running the Design Example
2.9. Compiling the Full Design and Programming the FPGA
2.5.1. Adding the Transceiver TX PLL IP Core
2.5.2. Adding the Reset Controller
2.5.3. Adding the Transceiver Reconfiguration Controller
2.5.4. Adding the Off-Chip Clean-Up PLL
2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.5.6. Transceiver PLL Calibration
2.5.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI Intel® FPGA IP Core Clocking Structure
3.3. CPRI Intel® FPGA IP Core Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI Intel® FPGA IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. Deterministic Latency and Delay Measurement and Calibration
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
5.1. INTR Register
5.2. L1_STATUS Register
5.3. L1_CONFIG Register
5.4. BIT_RATE_CONFIG Register
5.5. PROT_VER Register
5.6. TX_SCR Register
5.7. RX_SCR Register
5.8. CM_CONFIG Register
5.9. CM_STATUS Register
5.10. START_UP_SEQ Register
5.11. START_UP_TIMER Register
5.12. FLSAR Register
5.13. CTRL_INDEX Register
5.14. TX_CTRL Register
5.15. RX_CTRL Register
5.16. RX_ERR Register
5.17. RX_BFN Register
5.18. LOOPBACK Register
5.19. TX_DELAY Register
5.20. RX_DELAY Register
5.21. TX_EX_DELAY Register
5.22. RX_EX_DELAY Register
5.23. ROUND_TRIP_DELAY Register
5.24. XCVR_BITSLIP Register
5.25. DELAY_CAL_STD_CTRL1 Register
5.26. DELAY_CAL_STD_CTRL2 Register
5.27. DELAY_CAL_STD_CTRL3 Register
5.28. DELAY_CAL_STD_CTRL4 Register
5.29. DELAY_CAL_STD_CTRL5 Register
5.30. DELAY_CAL_STD_STATUS Register
5.31. DELAY_CAL_RTD Register
5.32. XCVR_TX_FIFO_DELAY Register
5.33. XCVR_RX_FIFO_DELAY Register
5.34. IP_INFO Register
5.35. DEBUG_STATUS Register
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3.17.3. Extended Delay Measurement Interface
Signal Name |
Direction |
Description |
---|---|---|
ex_delay_clk | Input | Clock for extended delay measurement. |
ex_delay_reset_n | Input | Resets the extended delay measurement block. This signal is active low. This reset signal is associated with the ex_delay_clk clock. |
latency_sclk | Input | Clock for extended delay measurement of Intel® Stratix® 10 hard FIFOs. You can (but need not) drive this clock at the same frequency as ex_delay_clk. |
latency_sreset_n | Input | Resets the extended delay measurement soft logic for the Intel® Stratix® 10 hard FIFOs. This signal is active low. This reset signal is associated with the latency_sclk clock. |