E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/29/2024
Public
Document Table of Contents

4.5. 100G Ethernet Dynamic Reconfiguration Design Example

The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example demonstrates a dynamic reconfiguration solution for Stratix® 10 devices using the E-Tile Hard IP for Ethernet Intel FPGA IP core with the following variants. The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example supports four PMA channels to create either a single 100G Ethernet channel, or four single 10G/25G Ethernet channels.

Table 46.  List of Supported Design Example Variants for 100G Ethernet Dynamic ReconfigurationAll variants support 156.25 MHz refclk and optional RS-FEC. The external AIB clocking, PTP, and asynchronous clock support are not available in the current implementation.
Base Operation Dynamic Reconfiguration Variants
100G MAC+PCS+(528,514)RS-FEC [NRZ] 100G MAC+PCS+(528,514)RS-FEC [NRZ]
100G MAC+PCS+(544,514)RS-FEC [PAM4]
100G MAC+PCS+(544,514)RS-FEC [NRZ]
100G MAC+PCS [NRZ]
4x25G MAC + PCS with RS-FEC [NRZ]
4x25G MAC + PCS [NRZ]

When a CSR reset occurs during or after a dynamic reconfiguration transition(DR), you must first perform a DR transition to the base operation mode (100G MAC+PCS+(528,514)RS-FEC [NRZ]) before proceeding to the other supported configurations. Failure to complete this step may result in errors during the DR transition to other supported configurations.

Figure 46. E-Tile 100G Dynamic Reconfiguration Transition Summary
Note: No direct Dynamic Reconfiguration transitions supported between the following speed/mode:
  • 100G MAC+PCS+(544,514)RS-FEC [PAM4] ←→ 4x25G MAC+PCS with RS-FEC [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [PAM4] ←→ 4x25G MAC+PCS [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [NRZ] ←→ 4x25G MAC+PCS with RS-FEC [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [NRZ] ←→ 4x25G MAC+PCS [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [PAM4] ←→ 100G MAC+PCS+(544,514)RS-FEC [NRZ]