E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

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Date 3/06/2022
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Design Examples 2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide Archives
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. CPRI Dynamic Reconfiguration Design Examples 4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation with Default HEX File 4.1.3.2. Running the Simulation with New HEX File 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. CPRI Dynamic Reconfiguration Design Examples x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. CPRI Design Example Interface Signals 4.3.5. CPRI Design Example Registers 4.3.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme
4.3.2. Simulation Design Examples x
4.3.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.3.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. 25G Ethernet to CPRI Design Example Interface Signals 4.4.5. 25G Ethernet to CPRI Design Examples Registers 4.4.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme 4.4.1.2. Reset
4.4.2. Simulation Design Examples x
4.4.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
1. About E-tile Hard IP Design Examples
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide Archives

4.5.8. Steps to Disable FEC

The following steps provide a procedure for disabling FEC for the 100G variant. For actual software implementation of the various steps, please refer to the software routines in the Design Example:
  1. FEC disabling:
    1. Bypass FEC - Write 0x0000 to FEC register 0x14 ([rsfec_top_rx_cfg]
    2. Disable FEC clock - Write 0x0000 to FEC register 0x04 ([rsfec_top_clk_cfg]
  2. Transceiver configuration:
    1. Write 0xCB to Transceiver channel register 0x4[7:0]
    2. Write 0x4C to Transceiver channel register 0x5[7:0]
    3. Write 0x0F to Transceiver channel register 0x6[7:0]
    4. Write 0xA6 to Transceiver channel register 0x7[7:0]
      Note: Repeat steps 2a to 2d for each Transceiver channel.
    5. Delay for 10,000 µs
    6. Write 0x00 to Transceiver channel register 0x200
    7. Write 0x00 to Transceiver channel register 0x201
    8. Write 0x00 to Transceiver channel register 0x202
    9. Write 0x81 to Transceiver channel register 0x203
    10. Wait for Transceiver channel register 0x207[7] is set to 1'b1
    11. Check that Transceiver channel register 0x207[0] is set 1'b0
    12. To enable PMA calibration when loading the new PMA settings, set bit 5 from Transceiver register 0x95
    13. To load initial PMA configuration, write 0x01 to Transceiver register 0x91
      Note: Repeat steps 2f to 2m for each Transceiver channel.
    14. Delay for 1000 µs
    15. To assert eio_sys_rst [Ethernet IO System Reset], write 0x0001 to MAC register 0x310
    16. Delay for 10,000 µs or use MAC signals to determine when it is ready
    17. To deassert eio_sys_rst [Ethernet IO System Reset], write 0x0000 to MAC register 0x310
    18. Delay for 1,000,000 µs or use MAC signals to determine when it is ready
  3. Rewrite MAC:
    1. Write 0x312C7 to MAC register 0x37a (Set Timer Window for Hi-BER Checks for CAUI-4 (4 x 25.78125 Gbps NRZ without FEC) configuration)
    2. Write 0x9FFD8028 to MAC register 0x40b (EHIP TX MAC Feature Configuration for CAUI-4 (4 x 25.78125 Gbps NRZ without FEC) configuration)
    3. Write 0x00000020 to MAC register 0x313 (Reset Sequencer RS-FEC disable)
    4. Set bits [3] and [9] of MAC register 0x30E (Use RX PCS Alignment)
    5. Delay for 10,000 µs
  4. Enable Internal Serial Loopback:
    1. Write 0x01 to Transceiver register 0x84
    2. Write 0x03 to Transceiver register 0x85
    3. Write 0x08 to Transceiver register 0x86
    4. Write 0x00 to Transceiver register 0x87
    5. Write 0x01 to Transceiver register 0x90
    6. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    7. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    8. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    Note: Repeat steps 4a to 4h for each Transceiver channel.
  5. Trigger PMA Adaptation:
    1. Write 0x18 to Transceiver register 0x84
    2. Write 0x01 to Transceiver register 0x85
    3. Write 0x2C to Transceiver register 0x86
    4. Write 0x00 to Transceiver register 0x87
    5. Write 0x01 to Transceiver register 0x90
    6. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    7. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    8. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    9. Write 0x00 to Transceiver register 0x84
    10. Write 0x00 to Transceiver register 0x85
    11. Write 0x6C to Transceiver register 0x86
    12. Write 0x00 to Transceiver register 0x87
    13. Write 0x01 to Transceiver register 0x90
    14. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    15. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    16. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    17. Write 0x01 to Transceiver register 0x84 (Enable Initial Adaptation)
    18. Write 0x00 to Transceiver register 0x85
    19. Write 0x0A to Transceiver register 0x86
    20. Write 0x00 to Transceiver register 0x87
    21. Write 0x01 to Transceiver register 0x90
    22. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    23. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    24. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
      Note: Repeat steps 5a to 5x for each Transceiver channel.
    25. Delay for 100 µs
    26. Write 0x00 to Transceiver register 0x84 (Check Initial Adaptation Status)
    27. Write 0x0B to Transceiver register 0x85
    28. Write 0x26 to Transceiver register 0x86
    29. Write 0x01 to Transceiver register 0x87
    30. Write 0x01 to Transceiver register 0x90
    31. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    32. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    33. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    34. Wait for Transceiver register 0x88 lower 4 bits are set to 1'b0 (indicates end of adaptation)
      Note: Repeat steps 5z to 5ah for each Transceiver channel.
    35. Delay for 100000 µs
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