E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

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Date 3/06/2022
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Design Examples 2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide Archives
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. CPRI Dynamic Reconfiguration Design Examples 4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation with Default HEX File 4.1.3.2. Running the Simulation with New HEX File 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. CPRI Dynamic Reconfiguration Design Examples x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. CPRI Design Example Interface Signals 4.3.5. CPRI Design Example Registers 4.3.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme
4.3.2. Simulation Design Examples x
4.3.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.3.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. 25G Ethernet to CPRI Design Example Interface Signals 4.4.5. 25G Ethernet to CPRI Design Examples Registers 4.4.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme 4.4.1.2. Reset
4.4.2. Simulation Design Examples x
4.4.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
1. About E-tile Hard IP Design Examples
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide Archives

4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components

Figure 44. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example High Level Block Diagram
The E-Tile Dynamic Reconfiguration Design Example includes the following components:
  • E-Tile Dynamic Reconfiguration Design Example core. The IP core consists of four 25G channels with optional RS-FEC or one 100G channel.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • Avalon® memory-mapped interface address decoder to decode reconfiguration address space for E-Tile Hard IP for Ethernet core and RS-FEC modules during reconfiguration accesses.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.

The hardware design example uses run_test command to initiate packet transmission from packet generator to the IP core. By default, the internal serial loopback is disabled in this design example. Use the loop_on command to enable the internal serial loopback. When you use the run_test command to run the hardware test in the design examples, the script tests 100GE with RS-FEC. Use the run_test_dr to run the hardware test to perform all reconfigurable switches. The client logic reads and print out the MAC statistic registers when the packet transmissions are complete.

The following sample script illustrates a reconfiguration sequence:

source hwtest/main.tcl
set BASE_EHIP 0x400
#DR to 25GNF
# configure dr_cfg_ch_en register
reg_write $BASE_EHIP 0x13 0xf;
# configure dr_cfg_fec_en register
reg_wrtie $BASE_EHIP 0x15 0x0;
# configure dr_control and trigger reconfig registers
reg_write 0x4009 0x1;
The following sample output illustrates a successful hardware test run for 100GE, switching from 100G Ethernet with RS-FEC to 100G Ethernet variation: 
% cd hwtest/altera_dr
% run_test_dr_sw "100G_rsfec" "100G_nofec"
-----------------------------------
----- Switching to 100G_nofec -----
-----------------------------------
- Checking init_adaptation status -
-----------------------------------
channel 0 init_adaptation status is 0
channel 1 init_adaptation status is 0
channel 2 init_adaptation status is 0
channel 3 init_adaptation status is 0

Running Traffic_test_100G_nofec test

 RX PHY Register Access: Checking Clock Frequencies (KHz) 
	REFCLK        :2 (KHZ) 
	TXCLK         :40283  (KHZ) 
	RXCLK         :40285  (KHZ) 
	TXRSCLK       :0  (KHZ) 
	RXRSCLK       :0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x000fffff 
 Rx PHY Fully Aligned?        0x00000001
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
 wait for phy lock 0, locked=0x00000001
 RX PHY Register Access: Checking Clock Frequencies (KHz) 
	REFCLK        :0 (KHZ) 
	TXCLK         :40283  (KHZ) 
	RXCLK         :40284  (KHZ) 
	TXRSCLK       :0  (KHZ) 
	RXRSCLK       :0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x00000000 
 Rx PHY Fully Aligned?        0x00000001
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
 
 RX PHY Register Access: Checking Clock Frequencies (KHz) 
	REFCLK        :1 (KHZ) 
	TXCLK         :40282  (KHZ) 
	RXCLK         :40285  (KHZ) 
	TXRSCLK       :0  (KHZ) 
	RXRSCLK       :0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x00000000 
 Rx PHY Fully Aligned?        0x00000001
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
 ==========================================================================================
                        STATISTICS FOR BASE 18688 (Rx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 14620 
65 - 127 Byte Frames             : 14148 
128 - 255 Byte Frames            : 28658 
256 - 511 Byte Frames            : 57110 
512 - 1023 Byte Frames           : 115595
1024 - 1518 Byte Frames          : 111182 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 3342259 
Rx Frame Starts                  : 3683572 
Multicast data  OK  Frame        : 0 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 3675761 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
 ==========================================================================================
                        STATISTICS FOR BASE 18432 (Tx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 14620 
65 - 127 Byte Frames             : 14148 
128 - 255 Byte Frames            : 28658 
256 - 511 Byte Frames            : 57110 
512 - 1023 Byte Frames           : 115595 
1024 - 1518 Byte Frames          : 111182
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 3342259 
Tx Frame Starts                  : 3683572 
Multicast data  OK  Frame        : 0 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 3675761 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0
Pause Control Frames             : 0
Traffic_test_100G_nofec: Pass
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